(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

Three-dimensional (3D) monolithic integration can enable higher density and has the potential to stack independently optimized layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited to be used as the top layer channel material in 3D monolithic integration along with Si/Si(Ge) FETs. A review of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

Resistive random-access memory (RRAM) constitutes a promising technology for next-generation memory architectures due to its simple structure, high on/off ratio, and processing-in-memory ability. Its compatibility with emerging monolithic 3D (M3D) integration enables extremely high density using monolithic inter-tier vias (MIVs). However, both RRAM and M3D are susceptible to high defect rates due to immature manufacturing processes and process variations. Fault diagnosis for M3D-integrated RRAM and MIVs is therefore necessary to facilitate yield learning. In this work, we present a detailed characterization of RRAM faulty behaviors in the presence of process variations and manufacturing defects. We develop a diagnosis procedure by identifying appropriate reference resistance based on RRAM characteristics to efficiently distinguish fault origins. Results show that the proposed solution is compatible with existing test algorithms to significantly improve diagnostic resolution without affecting fault coverage.

Monolithic three-dimensional (3D) integration enables the most fine-grained integration of transistors by stacking very thin layers and fabricating monolithic inter-layer vias as small as local vias. Thus, monolithic 3D integration is expected to provide a higher degree of wirelength reduction, performance improvement, and power saving. Due to the prospective properties of the monolithic 3D integration technology, research on multilayer monolithic 3D integration that stacks more than two device layers is also ongoing. In this paper, we propose an algorithm that optimizes dynamic power consumption of gate-level monolithic 3D ICs. Under the same timing constraints, our algorithm reduces dynamic power consumption more effectively than a uniform-scaling-based placement algorithm. We also design multi-tier monolithic 3D ICs and show that our algorithm outperforms the uniform-scaling-based placement algorithm by 11.4% on average.

The photonics landscape encompasses a wide scope of material platforms, each optimized for specific functionalities, yet no platform meets the demands of all current and evolving photonic applications. Although combining integrated-photonics materials enhances overall capability, such as unifying nonlinear optics, low-loss passive devices and electro-optics, material and process compatibility remains a major challenge. Here we introduce full-wafer, monolithic 3D integration of tantalum pentoxide (Ta2O5, hereafter tantala1) photonics directly onto a patterned substrate, demonstrated here with thin-film lithium niobate2. Tantala's unique properties, importantly room-temperature deposition, moderate-temperature annealing and low residual stress in thick films optimized for phase matching, make it well suited for monolithic 3D integration without compromising substrate performance or compatibility. We demonstrate low-loss, high-quality-factor microresonators and nanophotonics in tantala, robust quasi-phase-matching in poled lithium niobate waveguides3, and efficient 3D interlayer routing. These capabilities enable us to demonstrate a rich palette of nonlinear frequency conversion processes, including χ(3) four-wave mixing for supercontinuum generation, optical parametric oscillation and dark-pulse microcomb generation in tantala microresonators and photonic crystal resonators, χ(2) second-harmonic generation in periodically poled lithium niobate, and combinations thereof.

Heterogeneous manycore architectures are the key to efficiently execute compute- and data-intensive applications. Through-silicon-via (TSV)-based 3D manycore system is a promising solution in this direction as it enables the integration of disparate computing cores on a single system. Recent industry trends show the viability of 3D integration in real products (e.g., Intel Lakefield SoC Architecture, the AMD Radeon R9 Fury X graphics card, and Xilinx Virtex-7 2000T/H580T, etc.). However, the achievable performance of conventional TSV-based 3D systems is ultimately bottlenecked by the horizontal wires (wires in each planar die). Moreover, current TSV 3D architectures suffer from thermal limitations. Hence, TSV-based architectures do not realize the full potential of 3D integration. Monolithic 3D (M3D) integration, a breakthrough technology to achieve “More Moore and More Than Moore,” opens up the possibility of designing cores and associated network routers using multiple layers by utilizing monolithic inter-tier vias (MIVs) and hence, reducing the effective wire length. Compared to TSV-based 3D integrated circuits (ICs), M3D offers the “true” benefits of vertical dimension for system integration: the size of an MIV used in M3D is over 100 × smaller than a TSV. This dramatic reduction in via size and the resulting increase in density opens up numerous opportunities for design optimizations in 3D manycore systems: designers can use up to millions of MIVs for ultra-fine-grained 3D optimization, where individual cores and routers can be spread across multiple tiers for extreme power and performance optimization. In this work, we demonstrate how M3D-enabled vertical core and uncore elements offer significant performance and thermal improvements in manycore heterogeneous architectures compared to its TSV-based counterpart. To overcome the difficult optimization challenges due to the large design space and complex interactions among the heterogeneous components (CPU, GPU, Last Level Cache, etc.) in a M3D-based manycore chip, we leverage novel design-space exploration algorithms to trade off different objectives. The proposed M3D-enabled heterogeneous architecture, called HeM3D , outperforms its state-of-the-art TSV-equivalent counterpart by up to 18.3% in execution time while being up to 19°C cooler.

This talk aims to unveil how to effectively and optimally design 3D circuits covering aspects from 3D stacking to monolithic integration. As first, an overview of physical design challenges with respect to conventional 2D circuits will be provided, followed by an in-depth look into the power and thermal integrity challenges and solutions. More specifically, design challenges related to power, signal and clock distribution will be covered and also present some of the current solutions. Secondly, an overview of the reliability concerns for 3D circuits and their mitigation techniques will be presented. The talk will conclude with current challenges and future directions for 3D physical design.

In this chapter, the architectural impact of the 3D enhanced memories and routing resources were carefully studied. The traditional FPGA architecture was enhanced by the technologies presented in the previous chapter. The envisaged technologies move devices in 3D. Devices can be passive (e.g. resistive phase-change memories) or active (e.g. monolithic 3D integration or vertical NWFET). Performance estimations were carried out by benchmarking simulations of the improved FPGA architecture. The benchmarking tool is based on standard tools and tuned according to the technological parameters. We showed that, implemented in FPGAs, the resistive configuration memory node, coupled to the routing structure, yields a delay reduction up to 51%, thanks to the reduction of dimensions and low on-resistance of PCMs. This result was also reached by the vertical NWFET technology, because of the ability to size a large transistor vertically without a large impact on the projected area. In this case, the critical path delay may be reduced up to 49% compared to the traditional scaled MOS. Regarding the area metric, the best improvement was reached by the vertical NWFET technology with an improvement of about 46%. Vertical NWFET technology allowed moving all the peripheral circuits above the IC. By opposition, the PCM technology leads to a much tighter area improvement of 13%. Indeed, this technology requires a large programming transistor per node.Among the different technologies, we should remark that 3D monolithic integration process yields in an area improvement of 21% on average and in a delay improvement of 22% on average. Such a technology represents a good trade-off process for short term micro-electronics evolutions.

We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C–350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

Since the invention of MOSFET in 1959, and CMOS in 1963, CMOS circuits emerged as the preferred technology for low power battery powered applications such as digital watches and portable instruments. Lithography scaling enabled CMOS to compete in high-performance computing subsequently. Dennard's 1974 summary on CMOS scaling principle further offered the microelectronics industry a scientific scaling direction according to Moore's Law. By 2005, Dennard scaling principle, however, largely broke down due to the subthreshold leakage on planar MOSFET which prevented the Vth, Vdd, and frequency to scale. Double-gate (SOI), and tri-gate (FinFET) were invented to allow the channel to be better controlled so carriers won't escape to the substrate. A gate-all-around (e.g.: nano-wire and nano-sheet) MOSFET has the channel surrounded by gate electrode with even better electrostatic control, leading to leakage reduction and improved carrier mobility. With multi nano-sheets, the effective W (W_eff) in a unit area is also improved, allowing moderate density scaling compared to FinFet devices. More improvement for CMOS scaling is on the horizon by the industry. ForkFET, which uses a barrier layer between PMOS and NMOS, allows the PMOS and NMOS to be placed closer to each other, thus improving transistor density and reducing interconnect RC between PMOS and NMOS. Complementary FET (CFET), which has PMOS and NMOS stacked on top of each other, reduces the interconnect between PMOS and NMOS significantly as the interconnect on vertical stacking is much shorter than horizontal wiring. Future technology advancement may allow more layers of MOSFETs to be manufactured monolithically (Monolithic 3D integration), when thermal and testability challenges are better solved [1]–[9].

Recent advances in emerging technologies such as monolithic 3D Integration (M3D-IC) and emerging non-volatile (eNVM) have enabled to embed logic operations in memory. This alleviates the memory wall challenges stemming from the time and power expended on migrating data in conventional Von Neumann computing paradigms. We propose a M3D SRAM dot-product engine for compute in-SRAM support used in applications such as matrix multiplication and artificial neural networks. In addition, we propose a novel computing in RRAM-based architecture to efficiently solve the computation intensity of sparse dot products. Specifically, the index assessment of sparse matrix-vector multiplication used in support vector machines (SVM). At maximum throughput, our proposed RRAM architecture achieves 11.3× speed up when compared against a near-memory accelerator.

ABSTRACTIntegrating 2D materials into 3D architectures can break through the physical limits of materials in advanced processes. However, challenges such as severe interfacial doping caused by dielectric deposition during vertical stacking processing have led to performance degradation in MoS2 3D gate-all-around (GAA) field-effect transistors (FETs), thereby severely hindering their large-scale integration. Here, we demonstrate a lossless monolithic 3D (M3D) integration process flow enabled by using an interface engineering strategy to achieve the highly uniform large-scale integration of multichannel MoS2 GAAFETs with ultrahigh current density. This strategy involves reducing interface states and dielectric doping by forming van der Waals contacts with MoS2 and creating hydrophilic surfaces for high-κ dielectric deposition via an Sb2O3 layer, thereby significantly improving the performance of the GAAFETs. The statistics of 112 GAA devices exhibit record-breaking performance, including an average on-state current density of 227 μA/μm with a peak value of >335 μA/μm, and an ideal minimum subthreshold swing approaching 60 mV/dec, all outperforming conventional back-gate transistors and other MoS2 3D FETs. Furthermore, Technology Computer Aided Design simulation confirms that gate-all-around transistors exhibit a 46% reduction in resistance capacitance delay compared with planar structures, further demonstrating enhanced gate control. This work establishes a manufacturing pathway for achieving the interface-doping-free deposition of gate dielectric layers, thereby addressing the performance-degradation issue caused by repeated processing steps in high-density M3D heterogeneous integration.

Monolithic three-dimensional (3D) integration enables revolutionary digital system architectures of computation immersed in memory. Vertically-stacked layers of logic circuits and memories, with nano-scale inter-layer vias (with the same pitch and dimensions as tight-pitched metal layer vias), provide massive connectivity between the layers. The nano-scale inter-layer vias are orders of magnitude denser than conventional through silicon vias (TSVs). Such digital system architectures can achieve significant performance and energy efficiency benefits compared to today's designs. The massive vertical connectivity makes such architectures particularly attractive for abundant-data applications that impose stringent requirements with respect to low-latency data processing, high-bandwidth data transfer, and energy-efficient storage of massive amounts of data. We present an overview of our progress toward realizing monolithic 3D ICs, enabled by recent advances in emerging nanotechnologies such as carbon nanotube field-effect transistors and emerging memory technologies such as Resistive RAMs and Spin-Transfer Torque RAMs.

Ultra High Density Logic Designs Using Monolithic 3D Integration

Currently, there is active research on oxide semiconductors suitable for the next-generation integration technology, Monolithic 3D Integration (M3D). Among back-end-of-line (BEOL) compatible material candidates, SnO2, with its high mobility and wide bandgap (3.6 eV), is extensively utilized in the fields of solar cells and displays, semiconductors benefiting from excellent power efficiency, high price competitiveness, and transparency. Furthermore, the fluorine-doped tin oxide (FTO) is a highly transparent and conductive semiconductor, serving as a Transparent Conducting Oxide (TCO) widely utilized in various electronic and optoelectronic devices.In this study, we fabricated SnO2 Thin Film Transistors (TFTs) utilizing SnO2 deposited by Thermal-Atomic Layer Deposition (T-ALD) as the channel layer. Additionally, the surface of the SnO2 in the Source/Drain regions was n+ doped through fluorination to enhance ohmic characteristics between the electrode and the channel layer. In this process, we have successfully fabricated SnO2 TFTs demonstrating excellent electrical characteristics, with a very high on/off current ratio exceeding 1013 and a low Subthreshold Swing (S.S) of 0.18 V/dec, achieved by effectively controlling the conductivity of SnO2. These results emphasize the potential of ALD SnO2 channels for high-performance transistors that are compatible with back-end-of-line processes in Si technology. Figure 1