(Invited) Homoepitaxial GaN Growth and Substrate-Dependent Effects

Vertical GaN power switch technology is expected to be utilized in next-generation medium to high voltage power converters due to the low ON-resistance and high breakdown voltage enabled by the improved critical electric field and mobility compared to Si and SiC-based devices. As large area substrates have become available by hydride vapor phase epitaxy (HVPE) and ammonothermal growth, the properties of nitrides are no longer dominated by defects introduced by heteroepitaxial growth, allowing recent realization of several fundamental vertical power devices, including diodes with edge termination, trench MOSFETs, and CAVETs. However, additional materials challenges are coming to the forefront that need to be understood and surmounted in order to allow vertical GaN power devices to achieve their full potential, notably the realization of repeatable thick drift layers with low background doping. To enable this, a deeper understanding of substrate preparation and the effects of the substrate and growth initiation on the characteristics of the epitaxial layers is required for MOCVD growth of homoepitaxial films. We investigate these effects on epi morphology, uniformity, and impurity incorporation by growing simultaneously on wafers from different vendors. The goal of this work is to detect and identify defects in GaN substrates with a series of quick, non-destructive, inexpensive techniques with capabilities of mapping whole wafers. We have characterized multiple substrates from over eight suppliers and the homoepitaxy grown on those substrates. All the substrates had nominally similar as-received specifications (resistivity, thickness, off-cut angle, bow, surface finish). The substrates were evaluated with a variety of techniques including Raman spectroscopy, photoluminescence, white light interferometry, and Nomarski imaging, enabling to detection of different concentrations of grain boundaries, sample impurities, point defects, v-shaped pits, polishing defects, crystal stress damage, and non-uniform insulating and conducive regions. The substrates can be characterized in two different categories: those with uniform characteristics, including carrier concentration, and those without. Comparing these results to those from homoepitaxial growth on the same wafers, the effects are both subtle and overt. Macroscopic surface morphology, which has shown a direct correlation to leakage current, copies and exaggerates that of the underlying substrate. Photoluminescence of the homoepitaxial surface along with Raman spectroscopy show that non-uniformities in the substrate carrier concentration can continue into the epitaxy. Following optical characterization, vertical Schottky diodes were fabricated to quickly evaluate device performance. While most of the films showed the ability to withstand high electric fields, those with more uniform properties in the substrate also showed more uniform electrical properties. These results show that the bulk substrates enable the path to high voltage vertical devices, but also show the significant influence that substrates can play in device performance.

To date, a majority of epitaxial layers for vertical gallium nitride (GaN) power Schottky diodes have been grown by metalorganic chemical vapor deposition. In this work, we investigate the electrical properties of vertical GaN Schottky diodes with drift layers grown by hydride vapor phase epitaxy (HVPE) on moderately-doped freestanding HVPE GaN substrates. Room temperature IV data is presented for devices tested where results for diode characteristics such as the breakdown voltage, Vb, specific on-resistance, Ron-sp, ideality factor, n, and barrier height, Φb, are measured for devices across the 1 cm × 1 cm sample. The smallest diodes, which are 30 μm in diameter, show the smallest specific on-resistance, whereas the breakdown voltage (defined as the voltage corresponding to a current of 10 mA cm−2) is independent of device size across the wafer. IV data show an average value of 1.06 ± 0.06 for n and 0.80 ± 0.04 eV for Φb with little variation across the wafer, suggesting a reasonable metal–semiconductor interface across the entire sample. For one of the 300 μm devices tested, we also examine the IV properties as function of temperature from 25 to 250 °C in increments of 25 °C and extract a zero temperature Φb of 0.908 eV and Richardson’s constant of 4.44 A cm−2 K−2 which is significantly less than the theoretical value of 26.9 A cm−2 K−2.

We have been developing the technology that enables us to grow high quality and large GaN single crystals for producing high quality GaN single crystal su bstrates using Na flux method. In 2 005, we have succeeded in the growth of 2-inch GaN substrates with low dislocation density (< 10 5 cm -2 ) by applying the Liquid Phase Epitaxy to the Na flux method. Recently, we reported that dislocati on density lower than the order of 10 4 cm -2 and the growth rate more than 20 um/h is achievable in the Na flux LPE. This achievement was due to introducing some new techniques; such as thermal convection, mechanical stirring, addition of carbon additive, development of new growth apparatus and so on, to the Na flux LPE. Keywords: GaN, Single crystal, Substrate, Na flux, LPE INTRODUCTION Some approaches such as the hydride vapor phase epitaxy (HVPE) [1-3], ammonothermal growth [4-6], high-pressure solution growth [7-9], and the Na flux [10-25] meth ods have been found to enable the growth of large and high-quality GaN single crystals. The realization of high-quality GaN single crystal substrates with large diameter is expected to bring about the next generation of highly efficient electronic devices. Although 2-inch GaN substrates synthesized by the HVPE method have already been commercially produced, the curvature and large dislocation density included in the crystal have been identified as serious problems for use in future devices. In contrast, the other solution growth methods mentioned above have achieved the growth of GaN crystals with low dislocation density. The high-pressure solution growth method initially demonstrated extremely low dislocation GaN crystals. In the Na flux method, significant reduction of dislocation density was confirmed by applying the liquid phase epitaxy (LPE) technique [22]. Most recently, ammonothermal growth, which has been considered as a disadvantageous method from the perspective of dislocation density, has achieved dislocation density on the order of 10

Gallium Nitride (GaN) and its alloys form a promising material system for optoelectronic and electronic devices. Heteroepitaxial growth of GaN on sapphire and SiC, while viable, introduces threading dislocations (between 1E8 – 1E11 cm^-2), mismatches in thermal expansion coefficients, and limitations on available growth orientations other than the polar, &lt;0001&gt; directions. With a push towards longer wavelengths, higher output powers at higher efficiencies with reduced droop for LEDs, non-polar and semi-polar oriented devices are becoming increasingly important, though need currently lacking, large area, bulk GaN substrates. A solution is the ammonothermal growth technique, which entails dissolving a GaN feedstock in a supercritical ammonia solution containing sodium (P &lt; 270 MPa, T = 500–600 °C) and re-crystallizing the material on a GaN seed. Improvements in growth rate are needed to reduce cost and increase throughput. To that end, an ultra high purity (UHP) growth environment was created within a typical Ni-Cr superalloy autoclave by introducing a silver capsule. 40 basic ammonothermal growth runs were performed on hydride vapor phase epitaxy (HVPE) GaN seed crystals. The capsule design significantly reduced concentrations of transition metals in the GaN crystals (&lt;1x1E17 cm^-3) while improving the transparency to α(450 nm) = 2.2 cm^-1. Total growth rates improved from 200 to 344130 μm/day for c-plane and from 34 to 4612 μm/day for m-plane growth. Degradation in crystal quality based on the full width at half maximum of the ω-rocking curve using X-ray diffraction when compared to the seed crystal was only observed for Ga-face growth on c-plane oriented seeds, presumably due to poor nucleation. Cracking in thick growth layers was observed due to strain originating from the HVPE seed crystals. Differences in the total system pressure profiles were analyzed and the observed pressure drop due to outward diffusion of hydrogen during growth was modeled.

New measurements of the index of refraction for free-standing samples of gallium nitride are reported. A simple dispersive prism technique is used to obtain the birefringent indices from 500 to 5100 nm, covering most of the transparency range of this wide band gap semiconductor. Millimeter thick samples prepared by both ammonothermal growth and hydride vapor phase epitaxy are found to have nearly identical refractive indices. The observed dispersion fits well to a two-pole Sellmeier equation with an estimated overall accuracy of ± 0.002. Our results are found to be in good agreement with previous visible and near-IR measurements on thin-film GaN samples, however we observed significantly less dispersion in the mid-IR. Moderate heating of the samples also provided a new determination of dn/dT.

With its wide bandgap and high critical field, GaN is a promising material for high power electronics. To date, most GaN films have been grown on foreign substrates such as sapphire or SiC. Lattice mismatch between the film and substrate leads to a large number of threading dislocations (~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> -10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ). These defects are thought to lead to poor device performance such as premature breakdown. Device properties are generally improved by growth of low-doped (<; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ) GaN layers on high conductivity freestanding hydride vapor phase epitaxy (HVPE) GaN substrates. However, these films still have a large number of dislocations ~ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . Dislocations are randomly oriented in both hetero and homoepitaxial films leading to a wide variation of material quality and thus device performance across the wafer. Recently, a true bulk GaN substrate became available using an ammonothermal growth technique. These substrates have both a low resistivity and low threading dislocation density. Growth of low-doped films on these bulk substrates can potentially address the problems of uniformity and premature breakdown in GaN power Schottky diodes.

Effect of reactor geometry and growth parameters on the uniformity and material properties of [formula omitted] grown by hydride vapor-phase epitaxy

Materials and processing issues in vertical GaN power electronics

Modelling electrical behaviour of nonuniform AlSi Schottky diodes

Low-temperature (350 °C) and high-pressure (1 MPa) steam annealing is effective for improving the characteristics of low-temperature-processed polycrystalline silicon thin film transistors (LTPS-TFTs) and their uniformity. We developed high-pressure annealing systems for 600×720 and 400×500 mm2 glass substrates, and investigated the annealing effects on the electrical properties of n-channel TFTs. The TFTs fabricated without high-pressure annealing have a low saturation mobility caused by the large amount of fixed oxide charge in SiO2, and a high threshold voltage (Vth) caused by the high trap density at the SiO2/Si interface. High-pressure steam annealing effectively reduces the amount of fixed oxide charge and the number of interface traps, resulting in the improvement of TFT properties. The crystal orientation of poly-Si strongly affects the interface trap density, which causes the nonuniformity of the TFT characteristics. High-pressure annealing also decreases the deviation of the trap density caused by the crystal orientation, and uniform electrical properties are achieved.

Silver nanowire (AgNWs) transparent conductive film (TCF) is considered to be the most favorable material to replace indium tin oxide (ITO) as the next-generation transparent conductive film. However, the disadvantages of AgNWs, such as easy oxidation and high wire-wire junction resistance, dramatically limit its commercial application. In this paper, moisture treatment was adopted, and water was dripped on the surface of AgNWs film or breathed on the surface so that the surface was covered with a layer of water vapor. The morphology of silver nanowire mesh nodes is complex, and the curvature is large. According to the capillary condensation theory, water molecules preferentially condense near the geometric surface with significant curvature. The capillary force is generated, making the wire-wire junction of AgNWs mesh bond tightly, resulting in good ohmic contact. The experimental results show that AgNWs-TCF treated by moisture has better conductivity, with an average sheet resistance of 20 Ω/sq and more uniform electrical properties. The bending test and adhesion test showed that AgNWs-TCF treated by moisture still exhibited good mechanical bending resistance and environmental stability.

We report the high-pressure growth of doped InP and In/sub 1-x/Ga/sub x/P crystals by the vertical gradient-freeze method modified with the addition of a submerged heater. The submerged heater, which fits closely into the growth ampoule, effectively isolates two melt zones during growth to provide a constant doping concentration or alloy composition in the lower one, and therefore also in the crystal. The upper melt is encapsulated with B/sub 2/O/sub 3/. Since the submerged heater suppresses melt convection, it should also reduce the twinning frequency that is so troublesome for InP growth. The density of defects that result from excessive hoop stresses should also be reduced due to the essentially planar isotherm that is created near the solid-liquid interface by the submerged heater. The payoff could be a greatly improved yield of nearly unstrained InP wafers with lower defect density and more uniform electrical properties.

Future one-dimensional electronics require single-crystalline semiconductor free-standing nanorods grown with uniform electrical properties. However, this is currently unrealistic as each crystallographic plane of a nanorod grows at unique incorporation rates of environmental dopants, which forms axial and lateral growth sectors with different carrier concentrations. Here we propose a series of techniques that micro-sample a free-standing nanorod of interest, fabricate its arbitrary cross-sections by controlling focused ion beam incidence orientation, and visualize its internal carrier concentration map. ZnO nanorods are grown by selective area homoepitaxy in precursor aqueous solution, each of which has a (0001):+c top-plane and six {1–100}:m side-planes. Near-band-edge cathodoluminescence nanospectroscopy evaluates carrier concentration map within a nanorod at high spatial resolution (60 nm) and high sensitivity. It also visualizes +c and m growth sectors at arbitrary nanorod cross-section and history of local transient growth events within each growth sector. Our technique paves the way for well-defined bottom-up nanoelectronics.

Low-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

We have evaluated specific on-state resistance (Ron,sp) and switching performance of various GaN power field-effect transistors (FETs) with 600 and 1200 V ratings using analytical calculation and numerical simulation. The normally-off GaN power FET family includes lateral p-GaN gate high electron mobility transistors (HEMTs), lateral metal-oxide-semiconductor (MOS) channel HEMTs, current aperture vertical electron transistors (CAVETs) and vertical U-shaped trench-gate MOS field-effect transistors (UMOSFETs). This study shows the advantages of vertical GaN power FETs over lateral GaN power HEMTs. These advantages include lower Ron,sp and smaller switching energy loss, especially at higher blocking voltages (1200 V). At 600 V, lateral P-GaN gate HEMTs are competitive with vertical power FETs. Vertical GaN CAVETs perform better than both lateral HEMTs and vertical UMOSFETs at both voltage ratings, benefiting from its lowest Ron*QG figure-of-merit.