Materials and processing issues in vertical GaN power electronics

We propose a new edge termination technique for high-voltage vertical GaN power devices using boron-ion implantation into a p-GaN epitaxial layer. The boron-implanted layer after annealing at 800 °C results in a half-conductive p-type layer that is applicable to junction termination extension (JTE). Fabricated vertical p-n diodes with the JTE layers show substantial increase in breakdown voltage (BV) via tuning of the boron concentration. The JTE length dependence of the BV and photoemission location demonstrate that the electric field relaxation near the edge can be controlled by the boron implantation conditions. High avalanche current immunity and positive temperature dependence of the BV are observed for the optimal structure. The maximum BV of 1400 V is near an ideal value for the donor concentration in the drift layer. The proposed JTE technique can be a strong candidate for robust power devices.

Vertical GaN power devices have emerged to become promising candidates for next-generation high power applications due to superior material properties such as high breakdown voltage, low on-resistance, and high mobility compared to devices based on Si and SiC. GaN-based p-n junction switching devices enable higher voltage power with significantly higher efficiencies with added advantages of systems with reduced size and weight. A technological limitation of GaN, however, has been the inability to achieve high p-type doping in a planar, vertical device. Here, we will focus on recent developments to achieve high p-type efficiency though ion implantation, novel high temperature annealing schemes, and the importance of defects and morphology in native substrates and epitaxial layers.Mg-implanted homoepitaxial GaN annealed at temperatures at or above 1400 °C eliminates the formation of inversion domains and leads to improved dopant activation efficiency. Extended defects in the form of inversion domains contain electrically inactive Mg after post-implantation annealing at temperatures as high as 1300 °C (one GPa N2 overpressure), which results in a low dopant activation efficiency. While residual defects, such as dislocation loops, still exist after annealing at and above 1400 °C, chemical analysis at multiple dislocation loops shows no sign of Mg segregation. Meanwhile, an overall decreasing trend in the dislocation loop size and density is observed after annealing at the higher temperatures and longer times. Earlier work addressing electrical measurements of these types of samples showed that annealing at ~1400 °C leads to a dopant activation efficiency that is an order of magnitude higher than that observed at 1300 °C. This work complements the earlier work by identifying the microscopic defects (inversion domains) which incorporate Mg, and points to the benefits, in terms of defect density and p-type dopant activation, of using higher temperature (1400 °C) annealing cycles to activate Mg in GaN.

Na-flux is a promising growth method for producing large-diameter GaN substrates with ultralow dislocation density, required for high-power-density vertical GaN power devices. However, the lateral growth behavior of GaN under near-thermodynamic-equilibrium conditions remains insufficiently understood. In this work, circular apertures were introduced into the GaN substrate by laser processing to deliberately induce lateral growth during Na-flux growth. GaN originating from the aperture edges coalesced toward the center, with coalescence preferentially along the ⟨112̅0⟩ in-plane direction, with {112̅2} semipolar facets exposed at the advancing growth front. Notably, GaN grown above the apertures exhibited an enhanced lateral growth rate independent of the underlying seed, termed freestanding epitaxy. Furthermore, the stress distribution and crystallographic orientation within the lateral growth regions were systematically investigated by Raman spectra and Lang X-ray topography, respectively. Defect-selective etching with molten NaOH-KOH revealed a drastic reduction in the threading dislocation density from ∼106 cm–2 to below 104 cm–2 in the freestanding epitaxial regions. These results demonstrate that GaN lateral growth can be effectively enhanced in the Na-flux method, providing a physical basis for the fabrication of ultralow-dislocation-density GaN substrates.

Vertical GaN power switch technology is expected to be utilized in next-generation medium to high voltage power converters due to the low ON-resistance and high breakdown voltage enabled by the improved critical electric field and mobility compared to Si and SiC-based devices. As large area substrates have become available by hydride vapor phase epitaxy (HVPE) and ammonothermal growth, the properties of nitrides are no longer dominated by defects introduced by heteroepitaxial growth, allowing recent realization of several fundamental vertical power devices, including diodes with edge termination, trench MOSFETs, and CAVETs. However, additional materials challenges are coming to the forefront that need to be understood and surmounted in order to allow vertical GaN power devices to achieve their full potential, notably the realization of repeatable thick drift layers with low background doping. To enable this, a deeper understanding of substrate preparation and the effects of the substrate and growth initiation on the characteristics of the epitaxial layers is required for MOCVD growth of homoepitaxial films. We investigate these effects on epi morphology, uniformity, and impurity incorporation by growing simultaneously on wafers from different vendors. The goal of this work is to detect and identify defects in GaN substrates with a series of quick, non-destructive, inexpensive techniques with capabilities of mapping whole wafers. We have characterized multiple substrates from over eight suppliers and the homoepitaxy grown on those substrates. All the substrates had nominally similar as-received specifications (resistivity, thickness, off-cut angle, bow, surface finish). The substrates were evaluated with a variety of techniques including Raman spectroscopy, photoluminescence, white light interferometry, and Nomarski imaging, enabling to detection of different concentrations of grain boundaries, sample impurities, point defects, v-shaped pits, polishing defects, crystal stress damage, and non-uniform insulating and conducive regions. The substrates can be characterized in two different categories: those with uniform characteristics, including carrier concentration, and those without. Comparing these results to those from homoepitaxial growth on the same wafers, the effects are both subtle and overt. Macroscopic surface morphology, which has shown a direct correlation to leakage current, copies and exaggerates that of the underlying substrate. Photoluminescence of the homoepitaxial surface along with Raman spectroscopy show that non-uniformities in the substrate carrier concentration can continue into the epitaxy. Following optical characterization, vertical Schottky diodes were fabricated to quickly evaluate device performance. While most of the films showed the ability to withstand high electric fields, those with more uniform properties in the substrate also showed more uniform electrical properties. These results show that the bulk substrates enable the path to high voltage vertical devices, but also show the significant influence that substrates can play in device performance.

We have evaluated specific on-state resistance (Ron,sp) and switching performance of various GaN power field-effect transistors (FETs) with 600 and 1200 V ratings using analytical calculation and numerical simulation. The normally-off GaN power FET family includes lateral p-GaN gate high electron mobility transistors (HEMTs), lateral metal-oxide-semiconductor (MOS) channel HEMTs, current aperture vertical electron transistors (CAVETs) and vertical U-shaped trench-gate MOS field-effect transistors (UMOSFETs). This study shows the advantages of vertical GaN power FETs over lateral GaN power HEMTs. These advantages include lower Ron,sp and smaller switching energy loss, especially at higher blocking voltages (1200 V). At 600 V, lateral P-GaN gate HEMTs are competitive with vertical power FETs. Vertical GaN CAVETs perform better than both lateral HEMTs and vertical UMOSFETs at both voltage ratings, benefiting from its lowest Ron*QG figure-of-merit.

Vertical GaN power switch technology is expected to be utilized in next-generation medium to high voltage power converters due to the low ON-resistance and high breakdown voltage enabled by the improved critical electric field and mobility compared to Si and SiC-based devices. As large area substrates have become available by hydride vapor phase epitaxy (HVPE) and ammonothermal growth, the properties of nitrides are no longer dominated by defects introduced by heteroepitaxial growth, allowing recent realization of several fundamental vertical power devices, including diodes with edge termination, trench MOSFETs, and CAVETs. However, additional materials challenges are coming to the forefront that need to be understood and surmounted in order to allow vertical GaN power devices to achieve their full potential, notably the realization of repeatable thick drift layers with low background doping. To enable this, a deeper understanding of substrate preparation and the effects of the substrate and growth initiation on the characteristics of the epitaxial layers is required for MOCVD growth of homoepitaxial films. We investigate these effects on epi morphology, uniformity, and impurity incorporation by growing simultaneously on wafers from different vendors. The goal of this work is to detect and identify defects in GaN substrates with a series of quick, non-destructive, inexpensive techniques with capabilities of mapping whole wafers. Four different substrates - three grown by hydride vapor phase epitaxy and the fourth by ammonothermal technique were obtained from multiple vendors. All had nominally similar as-received specifications (resistivity, thickness, off-cut angle, bow, surface finish). The substrates were evaluated with a variety of techniques including Raman spectroscopy, photoluminescence, white light interferometry, and Nomarski imaging, enabling to detection of different concentrations of grain boundaries, sample impurities, point defects, v-shaped pits, polishing defects, crystal stress damage, and non-uniform insulating and conducive regions. Comparing these results to those from homoepitaxial growth on the same wafers, the effects are both subtle and overt. Macroscopic surface morphology, which has shown a direct correlation to leakage current, copies and exaggerates that of the underlying substrate. Donor incorporation in the epitaxy is relatively uniform, regardless of the substrate doping. However, homoepitaxy on substrates with inhomogeneous impurity incorporation did show some near band edge broadening by PL. Carbon incorporation varied with substrate offcut angle, which is supported by DFT calculations. All interfaces between epitaxy and substrate have a large Si peak, which requires further study. Following optical characterization, vertical Schottky diodes were fabricated to quickly evaluate device performance. While most of the films showed the ability to withstand high electric fields, those with more uniform properties in the substrate also showed more uniform electrical properties. These results show that the bulk substrates enable the path to high voltage vertical devices, but also show the significant influence that substrates can play in device performance.

In this work, we develop highly efficient ET schemes based on a selective-area processing methodology that can effectively stymie device leakage, resulting in reliable device operation. In particular, we demonstrate plasma-assisted molecular-beam epitaxy (PAMBE) facilitated silicon nitride shadowed selective-area growth (SNS-SAG) technique, capable of producing smooth GaN interfaces and sidewalls as an enabling technology for high-performance vertical GaN power devices. SNS-SAG is shown to reduce leakage current by at least four orders of magnitude compared to a dry etched device. Floating guard ring (FGR) and junction termination extension (JTE) based ET designs for GaN p-i-n diodes for punchthrough operation have been simulated and analyzed in order to develop SNS-SAG compatible space-modulated junction termination extension (SM-JTE) schemes capable of achieving maximum reverse blocking efficiency >98% while maintaining a wide doping window of up to $\sim \,\,5\times 10^{17}$ cm−3 at a minimum reverse blocking efficiency of ~ 90% extending well into high 1017cm−3 range ( $\sim \,\,8\times 10^{17}$ cm−3). In conjunction with the proposed SNS-SAG technique, SM-JTE schemes have the prospects to offer reliable GaN vertical power device operation.

Developing dielectric capacitors with both a high power density and a high energy density for application in power electronics has been a long-standing challenge. Glass-ceramics offer the potential of retaining the high relative permittivity of ceramics and at the same time of exhibiting the high dielectric breakdown strength and fast charge/discharge rate of glasses, thus producing concurrently high power and energy densities in a single material. In this work, glass-ceramics are fabricated to achieve simultaneously high power and energy densities, high efficiency, and thermal stability by tuning the glass crystallization process via a suitable nucleating agent and a high oxygen partial pressure. Under the same practical charge-discharge test conditions, the as-prepared glass-ceramics combine the high energy density of ceramics and ultrafast discharge rate of glasses, producing the highest power density among glass- and ceramic-based dielectric materials. This work demonstrates the significant potential of achieving both high power and energy densities in glass-ceramics by optimizing the glass crystallization process.

Gallium nitride (GaN) has emerged as one of the most attractive base materials for next-generation high-power and high-frequency electronic devices. Recent efforts have focused on realizing vertical power device structures such as in situ oxide, GaN interlayer based vertical trench metal–oxide–semiconductor field-effect transistors (OG-FETs). Unfortunately, the higher-power density of GaN electronics inevitably leads to considerable device self-heating which impacts device performance and reliability. Halide vapor-phase epitaxy (HVPE) is currently the most common approach for manufacturing commercial GaN substrates used to build vertical GaN transistors. Vertical device structures consist of GaN layers of diverse doping levels. Hence, it is of crucial importance to measure and understand how the dopant type (Si, Fe, and Mg), doping level, and crystal quality alter the thermal conductivity of HVPE-grown bulk GaN. In this work, a steady-state thermoreflectance (SSTR) technique was used to measure the thermal conductivity of HVPE-grown GaN substrates employing different doping schemes and levels. Structural and electrical characterization methods including X-ray diffraction (XRD), secondary-ion mass spectrometry (SIMS), Raman spectroscopy, and Hall-effect measurements were used to determine and compare the GaN crystal quality, dislocation density, doping level, and carrier concentration. Using this comprehensive suite of characterization methods, the interrelation among structural/electrical parameters and the thermal conductivity of bulk GaN substrates was investigated. While doping is evidenced to reduce the GaN thermal conductivity, the highest thermal conductivity (201 W/mK) is observed in a heavily Si-doped (1–5.00 × 1018 cm−3) substrate with the highest crystalline quality. This suggests that phonon-dislocation scattering dominates over phonon-impurity scattering in the tested HVPE-grown bulk GaN substrates. The results provide useful information for designing thermal management solutions for vertical GaN power electronic devices.

1.7-kV vertical GaN p-n diode with triple-zone graded junction termination extension formed by ion-implantation

Till date, fabrication of piezoelectric nanogenerator (PNG) with highly durable, high power density, and high energy conversion efficiency is of great concern. Here a flexible, sensitive, cost effective hybrid piezoelectric nanogenerator (HPNG) developed by integrating flexible steel woven fabric electrodes into poly(vinylidene fluoride) (PVDF)/aluminum oxides decorated reduced graphene oxide (AlO‐rGO) nanocomposite film is reported where AlO‐rGO acts as nucleating agent for electroactive β‐phase formation. The HPNG exhibits reliable energy harvesting performance with high output, fast charging capability, and high durability compared with previously reported PVDF based PNGs. This HPNG is capable for harvesting energy from a variety and easy accessible biomechanical and mechanical energy sources such as, body movements (e.g., hand folding, jogging, heel pressing, and foot striking, etc.) and machine vibration. The HPNG exhibits high output power density and energy conversion efficiency, facilitating direct light on different color of several commercial light‐emitting diodes instantly and powers up many portable electronic devices like wrist watch, calculator, speaker, and mobile liquid crystal display (LCD) screen through capacitor charging. More importantly, HPNG retains its performance after long compression cycles (≈158 400), demonstrating great promise as a piezoelectric energy harvester toward practical applications in harvesting biomechanical and mechanical energy for self‐powered systems.

Selective Area Regrowth and Doping for Vertical GaN Power Devices

We propose a new edge termination technique for high-voltage vertical GaN power devices using boron-ion implantation into a p-GaN epitaxial layer. The boron-implanted layer after annealing at 800°C results in a half-conductive p-type layer that is applicable to junction termination extension (JTE). The maximum breakdown voltage of 1400 V was near an ideal value for the donor concentration in the drift layer. High avalanche current immunity was observed for the optimal structure. In wafer-scale fabrication of the p-n diodes on a 4-inch free-standing GaN substrate, good reverse characteristics are observed across the wafer. The proposed JTE technique has high potential for wafer-scale fabrication of robust and highly efficient vertical GaN devices.

GaN power transistors have emerged as a promising solution for high-power (>1kV) and high-frequency (>100 kHz) applications due to GaN’s material properties, including wide bandgap (3.4eV), high critical electric field (3.3 MV/cm) and an electron saturation rate which is 2.8 times that of silicon [1]. Both vertical and lateral power transistor configurations require a MIS gate structure, which includes the deposition of a dielectric layer, most often Al2O3. However, the performance of these devices is significantly influenced by the quality of the dielectric/GaN interface and the choice of gate dielectric [2].For this reason, surface preparation is critical to minimize interface trap density by reducing defects and impurities prior to dielectric deposition, and thus enhancing electrical performance and stability. The search for an effective surface treatment method, whether wet or dry, has been the focus of several studies [3]. However, many factors were not taken into consideration, such as the re-oxidation of GaN prior to dielectric deposition, the dependence of interface quality on the nature of the dielectric and its thickness, hence the need for an in-situ approach that treats interface and dielectric quality in a non-separate way.In this study, we first focus on in-situ atomic layer cleaning of the GaN surface using different plasma atmospheres (NH3, Ar, H2, N2) to investigate their impact on the interface under the same conditions with a reference dielectric Al2O3. Secondly, we explore the integration of an ALD-ternary high-K dielectric, AlSiO, through two approaches, both conducted without an air break to preserve the benefits of plasma cleaning. The approaches are either multilayer mode (Al2O3/SiO2) or mixed mode.To assess interface quality and dielectric performance, MOS capacitors (MOSCAPs) are fabricated. Their characterization is conducted through capacitance-voltage (C-V) and current-voltage (I-V) measurements, complemented by hard X-ray photoelectron spectroscopy (HAXPES).Our goal is to achieve a lower hysteresis (ΔVFB) < 50 mV and a flat band voltage (VFB) shifting towards 0V for the Al2O3/GaN interface and positive values for the AlSiO/GaN interface. Our results demonstrate significant improvements in ΔVFB. Among the different plasma cleaning atmospheres tested, NH3/N2 plasma treatment at low power was selected as the optimal choice, offering a balance between minimizing ΔVFB and achieving a VFB close to 0V.This was followed by the deposition of AlSiO with a low-silicon matrix, the comparison between the effectiveness of both approaches (Mixed and multilayer) is still ongoing .These process conditions will be further used for 200mm vertical power transistors to investigate their impact on device performance.[1] Catherine Langpoklakpam et al., « Vertical GaN MOSFET Power Devices », Micromachines 14, no 10 (octobre 2023): 1937, https://doi.org/10.3390/mi14101937.[2] Anthony Calzolaro, Thomas Mikolajick, et Andre Wachowiak, « Status of Aluminum Oxide Gate Dielectric Technology for Insulated-Gate GaN-Based Devices », Materials 15, no 3 (janvier 2022): 791, https://doi.org/10.3390/ma15030791.[3] Yutao Cai et al., « Effect of Surface Treatment on Electrical Properties of GaN Metal–Insulator–Semiconductor Devices with Al2O3 Gate Dielectric », Japanese Journal of Applied Physics 59, no 4 (mars 2020): 041001, https://doi.org/10.35848/1347-4065/ab7863.

Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications. Being still in an early development phase, vertical GaN devices are yet to be fully optimized and require careful studies to foster their development. In this work, we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs (TMOS’s) provided by TCAD simulations, enhancing the dependability of the adopted process optimization approaches. Specifically, two different TMOS devices are compared in terms of transfer-curve hysteresis (H) and subthreshold slope (SS), showing a ≈ 75% H reduction along with a ≈ 30% SS decrease. Simulations allow attributing the achieved improvements to a decrease in the border and interface traps, respectively. A sensitivity analysis is also carried out, allowing to quantify the additional trap density reduction required to minimize both figures of merit.