Optimization of ALD High-K Dielectric/GaN Interface for GaN Power Transistors

Correlation of PECVD SiOxNy dielectric layer structural properties and Si/SiOxNy/Al capacitors interface electrical properties

The quality of the fibre-matrix interface is significant for the application of natural fibre as reinforcement fibre for plastics. Chemical treatments can be used to optimise this interface. The modification methods are of different efficiency for the adhesion between matrix and fibre. In the present study, the effect of chemical surface treatment on mechanical properties of natural fibre was discussed. The effects of surface treatment and concentration on natural fibre were evaluated by means of strength distribution, elastic modulus and scanning electron microscopy.

This letter presents the first experimental study on capacitances, charges, and power-switching figure of merits (FOM) for a large-area vertical GaN power transistor. A 1.2-kV, 5-A GaN vertical power FinFET was demonstrated in a chip area of 0.45 mm2, with a specific on-resistance of 2.1 $\text{m}\Omega \cdot \textsf {cm}^{\textsf {2}}$ and a threshold voltage of 1.3 V. Device junction capacitances were characterized and their main components were identified. This was used to calculate the switching charges and practical switching frequencies. Device FOMs were then derived that take into account the trade-offs between the conduction and switching power losses. Our GaN vertical FinFETs exhibit high-frequency (~MHz) switching capabilities and superior switching FOMs when compared with commercial 0.9-1.2-kV Si and SiC power transistors. This letter shows the great potential of GaN vertical FinFETs for next-generation medium-voltage power electronics.

Vertical GaN power switch technology is expected to be utilized in next-generation medium to high voltage power converters due to the low ON-resistance and high breakdown voltage enabled by the improved critical electric field and mobility compared to Si and SiC-based devices. As large area substrates have become available by hydride vapor phase epitaxy (HVPE) and ammonothermal growth, the properties of nitrides are no longer dominated by defects introduced by heteroepitaxial growth, allowing recent realization of several fundamental vertical power devices, including diodes with edge termination, trench MOSFETs, and CAVETs. However, additional materials challenges are coming to the forefront that need to be understood and surmounted in order to allow vertical GaN power devices to achieve their full potential, notably the realization of repeatable thick drift layers with low background doping. To enable this, a deeper understanding of substrate preparation and the effects of the substrate and growth initiation on the characteristics of the epitaxial layers is required for MOCVD growth of homoepitaxial films. We investigate these effects on epi morphology, uniformity, and impurity incorporation by growing simultaneously on wafers from different vendors. The goal of this work is to detect and identify defects in GaN substrates with a series of quick, non-destructive, inexpensive techniques with capabilities of mapping whole wafers. We have characterized multiple substrates from over eight suppliers and the homoepitaxy grown on those substrates. All the substrates had nominally similar as-received specifications (resistivity, thickness, off-cut angle, bow, surface finish). The substrates were evaluated with a variety of techniques including Raman spectroscopy, photoluminescence, white light interferometry, and Nomarski imaging, enabling to detection of different concentrations of grain boundaries, sample impurities, point defects, v-shaped pits, polishing defects, crystal stress damage, and non-uniform insulating and conducive regions. The substrates can be characterized in two different categories: those with uniform characteristics, including carrier concentration, and those without. Comparing these results to those from homoepitaxial growth on the same wafers, the effects are both subtle and overt. Macroscopic surface morphology, which has shown a direct correlation to leakage current, copies and exaggerates that of the underlying substrate. Photoluminescence of the homoepitaxial surface along with Raman spectroscopy show that non-uniformities in the substrate carrier concentration can continue into the epitaxy. Following optical characterization, vertical Schottky diodes were fabricated to quickly evaluate device performance. While most of the films showed the ability to withstand high electric fields, those with more uniform properties in the substrate also showed more uniform electrical properties. These results show that the bulk substrates enable the path to high voltage vertical devices, but also show the significant influence that substrates can play in device performance.

Advanced metal-oxide-semiconductor (MOS) and metal-insulator-semiconductor (MIS) devices employ ultra thin dielectric gate layers. The physical dimensions are in the range of single digit to double digit nanometers. The effective oxide thickness (EOT) is significantly less than 10 nm. Pure SiO2 or combinations of SiO2and SiN layers are typically used as gate dielectrics. High dielectric constant materials (high-k dielectrics) and metal gates are also frequently used, depending on chip design.Physical dimensions of dielectric layer(s) are typically measured using ellipsometry and high resolution cross-section transmission microscopy (HRXTEM). Electrical characteristics are typically characterized using either contact or non-contact C-V and I-V measurements tools. Non-contact characterization techniques are generally preferred for in-line monitoring applications. However, spatial resolution of non-contact C-V and I-V measurement techniques is in the range of a few millimeters, which are 3 orders of magnitude larger than typical dimensions of actual devices. High spatial resolution, non-contact dielectric/Si interface quality characterization techniques must be developed.In this paper, ultra thin (~7 nm) SiO2/Si and ultra thin SiN/SiO2/Si wafers were prepared by low pressure thermal chemical vapor deposition (CVD) and thermal oxidation. Dielectric/Si interface quality was characterized by room temperature spectroscopic photoluminescence (PL) measurements. The PL intensity and spectra from Si were measured under different excitation wavelengths which have different probing depths. PL is an optical characterization technique which does not require any sample preparation and physical contact. Typical spatial resolution is in the range of a few microns. Small variations in dielectric/Si interface quality modulates electronic carrier behaviors significantly which results in large variations in PL intensity and spectra. Significant variations in PL intensity and spectra were measured from ultra thin (~7 nm) SiO2/Si wafers prepared by and low pressure thermal CVD and thermal oxidation. Si wafers with thermal oxide films generally showed significantly stronger PL intensity than Si wafers with thermal CVD grown oxide films (Fig. 1). Trends in PL intensity and spectra indicate the SiO2/Si interface quality of the thermally oxidized SiO2/Si is superior to that of the thermal CVD grown SiO2/Si (Fig. 2). PL characterization is found to be very sensitive to the integrity of dielectric/Si interface and thus, is promising as an in-line, non-contact interface quality monitoring technique.The excitation wavelength dependence of PL intensity and spectra of SiO2/Si and SiN/SiO2/Si will be discussed along with conventional physical and electrical characterization results.

We propose a new edge termination technique for high-voltage vertical GaN power devices using boron-ion implantation into a p-GaN epitaxial layer. The boron-implanted layer after annealing at 800 °C results in a half-conductive p-type layer that is applicable to junction termination extension (JTE). Fabricated vertical p-n diodes with the JTE layers show substantial increase in breakdown voltage (BV) via tuning of the boron concentration. The JTE length dependence of the BV and photoemission location demonstrate that the electric field relaxation near the edge can be controlled by the boron implantation conditions. High avalanche current immunity and positive temperature dependence of the BV are observed for the optimal structure. The maximum BV of 1400 V is near an ideal value for the donor concentration in the drift layer. The proposed JTE technique can be a strong candidate for robust power devices.

In this work, we develop highly efficient ET schemes based on a selective-area processing methodology that can effectively stymie device leakage, resulting in reliable device operation. In particular, we demonstrate plasma-assisted molecular-beam epitaxy (PAMBE) facilitated silicon nitride shadowed selective-area growth (SNS-SAG) technique, capable of producing smooth GaN interfaces and sidewalls as an enabling technology for high-performance vertical GaN power devices. SNS-SAG is shown to reduce leakage current by at least four orders of magnitude compared to a dry etched device. Floating guard ring (FGR) and junction termination extension (JTE) based ET designs for GaN p-i-n diodes for punchthrough operation have been simulated and analyzed in order to develop SNS-SAG compatible space-modulated junction termination extension (SM-JTE) schemes capable of achieving maximum reverse blocking efficiency >98% while maintaining a wide doping window of up to $\sim \,\,5\times 10^{17}$ cm−3 at a minimum reverse blocking efficiency of ~ 90% extending well into high 1017cm−3 range ( $\sim \,\,8\times 10^{17}$ cm−3). In conjunction with the proposed SNS-SAG technique, SM-JTE schemes have the prospects to offer reliable GaN vertical power device operation.

Surface preparation and corrosion behavior of titanium alloys were studied; both topics deal with the formation of surface oxide films. When metals are prepared for surgical implant use, an effort is made to produce an optimum surface. Effects of the surface treatments on surface morphology, surface film composition, and structure are shown in transmission electron photomicrographs and electron diffraction patterns. Roughened surfaces were produced, and surface films of titanium oxide (TiO) or titanium dioxide (TiO2) or both occurred on some specimens. Sodium titanate (NaO · xTiO2) occurred on the specimens washed in sodium hydroxide (NaOH) solution. Open circuit potential versus time curves have been measured to show some electrochemical effects of various surface treatments. The results show that titanium alloys immersed in Hanks' physiological solution reach the same final open-circuit potential after approximately two weeks' exposure regardless of prior surface treatment. Measurements of the anodic polarization behavior of titanium alloys and other surgical implant alloys show the effects of alloy composition and the testing solution on the passive region and breakdown potentials of these materials. In general, for titanium alloys, the differences are not great, but the presence of nickel results in a significant lowering of the breakdown potential. The materials studied were titanium, Ti-6Al-4V, titanium-nickel (memory alloy), Ti-13Cu-4Ni, and Ti-4.5Al-5Mo-1.5Cr. In all cases titanium materials are more corrosion resistant in Hanks' solution than cobalt-chromium-molybdenum Type 316L stainless steel, or cobalt-nickel-chromium alloys. Repassivation measurements show the rapid formation and the high degree of stability of the protective film on titanium and titanium alloys.

Carrier mobility of MoS 2 transistor can be greatly improved by screening the Columbic scattering by a high-k gate dielectric. In this work, different TiO 2 amounts are incorporated into HfO 2 to form Hf 1-x Ti x O gate dielectrics to investigate its effects on the electrical properties of MoS 2 transistor. It is found that enhanced carrier mobility and decreased gate leakage current can be achieved by optimizing the Ti content, i.e. with ${\rm{Hf}}_{0.9}{\rm{Ti}}_{0.1}O (x = 0.1)$ as the gate dielectric, the device exhibits the highest carrier mobility of 31.5 ${\rm{cm}}^{2}/Vs$, which is $ 1.3\times$ improvement as compared to the sample with HfO 2 as gate dielectric $(24.1 {\rm{cm}}^{2}/Vs)$. The main mechanism lies in that Hf 1-x Ti x O has higher k value than HfO 2 to increase the Coulomb screening effect and thus carrier mobility. However, with further increase of Ti content, e.g. ${\rm{Hf}}_{0.85}{\rm{Ti}}_{0.15}O (x= 0.15)$, the device exhibits larger off current and degraded subthreshold swing. This is probably attributed to Ti-related oxide traps, a decreased conduction-band offset between ${\rm{Hf}}_{0.85}{\rm{Ti}}_{0.15}{\rm{O}}$ and MoS 2 , and degraded $MoS_{2}/{\rm{Hf}}_{1-x}{\rm{Ti}}_{x}{\rm{O}}$ interface quality.

Materials and processing issues in vertical GaN power electronics

Vertical gallium nitride (GaN) power devices have attracted increased attention due to their superior high-voltage and high-current capacity as well as easier thermal management than lateral GaN high electron mobility transistors. Vertical GaN devices are promising candidates for next-generation power electronics in electric vehicles, data centers, smart grids and renewable energy process. The use of low-cost foreign substrates such as silicon (Si) substrates, instead of the expensive free-standing GaN substrates, could greatly trim material cost and enable large-diameter wafer processing while maintaining high device performance. This review illustrates recent progress in material epitaxy, device design, device physics and processing technologies for the development of vertical GaN power devices on low-cost foreign substrates. Although the device technologies are still at the early stage of development, state-of-the-art vertical GaN-on-Si power diodes have already shown superior Baliga’s figure of merit than commercial SiC and Si power devices at the voltage classes beyond 600 V. Furthermore, we unveil the design space of vertical GaN power devices on native and different foreign substrates, from the analysis of the impact of dislocation and defects on device performance. We conclude by identifying the application space, current challenges and exciting research opportunities in this very dynamic research field.

Recent advances in the design, fabrication, robustness and reliability of high-voltage vertical and lateral smart power devices in wide and extreme bandgap semiconductors (particularly SiC and GaN) [1] are presented and discussed. The basic device structures and their refinements, with respect to their potential and experimental performance, are evaluated and compared to their Si or GaAs counterparts. Key processing technologies (such as MOS and heterojunction) needed for the performance and manufacturing of these power devices are examined with their compatibility with commercial silicon foundry capabilities. The robustness and reliability of present commercial discrete power transistors (like threshold stability, current collapse, HTRB) are assessed. Future directions and challenges for the widespread adoption of this emerging power device technology are identified.[1] T.P. Chow, I. Omura, M. Higashiwaki, H. Kawarada, and V. Pala, IEEE Trans. Electron Devices, 64, 856 (2017).

Three-dimensional vertical Si nanowire MOS capacitor model structure for the study of electrical versus geometrical Si nanowire characteristics

Vertical GaN power switch technology is expected to be utilized in next-generation medium to high voltage power converters due to the low ON-resistance and high breakdown voltage enabled by the improved critical electric field and mobility compared to Si and SiC-based devices. As large area substrates have become available by hydride vapor phase epitaxy (HVPE) and ammonothermal growth, the properties of nitrides are no longer dominated by defects introduced by heteroepitaxial growth, allowing recent realization of several fundamental vertical power devices, including diodes with edge termination, trench MOSFETs, and CAVETs. However, additional materials challenges are coming to the forefront that need to be understood and surmounted in order to allow vertical GaN power devices to achieve their full potential, notably the realization of repeatable thick drift layers with low background doping. To enable this, a deeper understanding of substrate preparation and the effects of the substrate and growth initiation on the characteristics of the epitaxial layers is required for MOCVD growth of homoepitaxial films. We investigate these effects on epi morphology, uniformity, and impurity incorporation by growing simultaneously on wafers from different vendors. The goal of this work is to detect and identify defects in GaN substrates with a series of quick, non-destructive, inexpensive techniques with capabilities of mapping whole wafers. Four different substrates - three grown by hydride vapor phase epitaxy and the fourth by ammonothermal technique were obtained from multiple vendors. All had nominally similar as-received specifications (resistivity, thickness, off-cut angle, bow, surface finish). The substrates were evaluated with a variety of techniques including Raman spectroscopy, photoluminescence, white light interferometry, and Nomarski imaging, enabling to detection of different concentrations of grain boundaries, sample impurities, point defects, v-shaped pits, polishing defects, crystal stress damage, and non-uniform insulating and conducive regions. Comparing these results to those from homoepitaxial growth on the same wafers, the effects are both subtle and overt. Macroscopic surface morphology, which has shown a direct correlation to leakage current, copies and exaggerates that of the underlying substrate. Donor incorporation in the epitaxy is relatively uniform, regardless of the substrate doping. However, homoepitaxy on substrates with inhomogeneous impurity incorporation did show some near band edge broadening by PL. Carbon incorporation varied with substrate offcut angle, which is supported by DFT calculations. All interfaces between epitaxy and substrate have a large Si peak, which requires further study. Following optical characterization, vertical Schottky diodes were fabricated to quickly evaluate device performance. While most of the films showed the ability to withstand high electric fields, those with more uniform properties in the substrate also showed more uniform electrical properties. These results show that the bulk substrates enable the path to high voltage vertical devices, but also show the significant influence that substrates can play in device performance.

GaN power transistors are attracting increasing attention for next-generation power switching applications. However, GaN power transistors should not be regarded as a direct replacement for silicon power metal–oxide–semiconductor field-effect transistors, since the unique properties of GaN power transistors require special treatment. In this work we review a unique and critical property of GaN power transistors, the dynamic threshold voltage (V th). GaN power transistors feature a p-GaN gate structure, while the gate metal contacts the p-GaN layer through a Schottky junction. This unique p-GaN gate structure is distinctively different from the silicon metal–oxide–semiconductor gate structure in that the p-GaN layer is actually a floating region without direct electrical contact to the external electrodes of the device. The floating p-GaN layer enables a charge storage process during the switching operation of a p-GaN gate high-electron-mobility transistor. Through carefully designed experiments, the strong correlation between charge storage and the dynamic V th shift has been revealed; this also serves as an approach to accurately predict the dynamic V th during switching operation. The influence of the dynamic V th on power switching applications is discussed. For example, with a positive dynamic V th shift, the reverse conduction voltage of a GaN power transistor is significantly increased, adding to the power loss. This positive V th shift also demands a sufficiently high gate drive voltage to ensure that the GaN power transistor can be fully turned on, which reduces the safety margin for the gate reliability of the device. To design a GaN based power switching circuit, accurate simulation of the device/circuit characteristics is necessary. Circuit simulations that do not consider the dynamic V th lead to a large deviation from the measurement circuit characteristics. We demonstrate that by incorporating the dynamic V th into the circuit model this deviation can be effectively eliminated.