Iterative Decoding of Low-Density Parity-Check Codes Over Compound Channels

Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.

Four new messages for decoding of low-density parity-check (LDPC) codes are proposed. An a posteriori probability ratio (APPR) message, an a posteriori probability (APP) message, and an a posteriori probability difference (APPD) message for variable and check nodes are derived for sum-product decoding of LDPC codes. Also, we propose a hybrid APPD-APPR message, which denotes a hybrid message with an APPD variable node message and APPR check node message. All the proposed messages require only addition, subtraction, multiplication, and division operations for decoding of LDPC codes. We show that the hybrid APPD-APPR message-passing has the lowest complexity among the proposed messages.

The linear programming (LP) decoding of Low-Density Parity-Check (LDPC) codes is widely concerned for its maximum likelihood (ML) features. It is that the ML decoding rule for LDPC codes can be relaxed to LP optimization problem. Therefore, this paper focus on an efficient algorithm called infeasible primal-dual interior-point (IPDIP) to solve the LP problem. In each iteration, the IPDIP algorithm obtains the predictor and corrector steps by solving the Karush-Kuhn-Tucker (KKT) equation twice. The predictor term is used to responsible for optimal solution and the corrector term keeps the current iteration away from the boundary of the feasible region. Furthermore, a modification of the centering parameter is developed to accelerate the convergence speed for the IPDIP algorithm. Simulation results of LP decoding demonstrate that the proposed IPDIP algorithm achieves beautiful bit error rate (BER) performance and good global convergence properties with less iteration number and time than other algorithms which only solve the KKT equation once by Newton method or use the not modified centering parameter.

Low-Density Parity-Check (LDPC) codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years. This paper describes two strategies to parallelize min-sum decoding of irregular LDPC codes. The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture (CUDA) to parallelize LDPC decoding on Graphics Processing Units (GPUs). Empirical studies on data with various scales show that the performance of these decoding processes is improved by these parallel strategies and the GPUs provide more efficient, fast implementation decoder.

The problem of low-complexity linear programming (LP) decoding of nonbinary low-density parity-check (LDPC) codes is considered, and an iterative LP decoding algorithm is presented. Results that were previously derived for binary LDPC codes are extended to the nonbinary case. Both simple and generalized nonbinary LDPC codes are considered. It is shown how the algorithm can be implemented efficiently using a finite-field fast Fourier transform. Then, the convergence rate of the algorithm is analyzed. The complexity of the algorithm scales linearly in the block length, and it can approximate, up to an arbitrarily small relative error, the objective function of the exact LP solution. When applied to a typical code from an appropriate nonbinary LDPC code ensemble, the algorithm can correct a constant fraction of errors in linear (in the block length) computational complexity. Computer experiments with the new iterative LP decoding algorithm show that, in the error floor region, it can have better performance compared to belief propagation decoding, with similar computational requirements.

The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by interconnect and the storage requirements. Here, the proposed layout-aware layered decoder architecture utilizes the data-reuse properties of min-sum, layered decoding and structured properties of array LDPC codes. This results in a significant reduction of logic and interconnects requirements of the decoder when compared to the state-of-the-art LDPC decoders. The ASIC implementation of the proposed fully parallel architecture achieves throughput of 4.6 Gbps (for a maximum of 15 iterations). The chip size is 2.3 mm times 2.3 mm in 0.13 micron technology

The layered decoding algorithm has recently been proposed as an efficient means for the decoding of low-density parity-check (LDPC) codes, thanks to the remarkable improvement in the convergence speed (2×) of the decoding process. However, pipelined semi-parallel decoders suffer from violations or "hazards" between consecutive updates, which not only violate the layered principle but also enforce the loops in the code, thus spoiling the error correction performance. This paper describes three different techniques to properly reschedule the decoding updates, based on the careful insertion of "idle" cycles, to prevent the hazards of the pipeline mechanism. Also, different semi-parallel architectures of a layered LDPC decoder suitable for use with such techniques are analyzed. Then, taking the LDPC codes for the wireless local area network (IEEE 802.11n) as a case study, a detailed analysis of the performance attained with the proposed techniques and architectures is reported, and results of the logic synthesis on a 65nm low-power CMOS technology are shown.

Decoding by alternating direction method of multipliers (ADMM) is a promising linear programming decoder for low-density parity-check (LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder. For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.

We consider communication over the binary erasure channel (BEC) using\nlow-density parity-check (LDPC) codes and belief propagation (BP) decoding. For\nfixed numbers of BP iterations, the bit error probability approaches a limit as\nblocklength tends to infinity, and the limit is obtained via density evolution.\nOn the other hand, the difference between the bit error probability of codes\nwith blocklength $n$ and that in the large blocklength limit is asymptotically\n$\\alpha(\\epsilon,t)/n + \\Theta(n^{-2})$ where $\\alpha(\\epsilon,t)$ denotes a\nspecific constant determined by the code ensemble considered, the number $t$ of\niterations, and the erasure probability $\\epsilon$ of the BEC. In this paper,\nwe derive a set of recursive formulas which allows evaluation of the constant\n$\\alpha(\\epsilon,t)$ for standard irregular ensembles. The dominant difference\n$\\alpha(\\epsilon,t)/n$ can be considered as effects of cycle-free and\nsingle-cycle structures of local graphs. Furthermore, it is confirmed via\nnumerical simulations that estimation of the bit error probability using\n$\\alpha(\\epsilon,t)$ is accurate even for small blocklengths.\n

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

The best known practical algorithm for the decoding of low-density parity-check (LDPC) codes is the iterative sum-product or belief propagation algorithm, operating on a Tanner graph (TG) of the code. Conventionally, in each iteration, all the symbol nodes and subsequently all the check nodes in the TG pass new messages to their neighbors (the so-called flooding schedule). We propose a new message-passing schedule, called schedule. Unlike flooding, the probabilistic schedule operates based on the structure of the TG, and probabilistically balances the frequency at which different symbol nodes update their outgoing messages in accordance with their girths. Our results show that, particularly for short block lengths, the new schedule offers a much better performance/complexity trade-off. For a particular example of a (1268,456) code, at no cost in complexity, the probabilistic schedule not only decreases both the bit and message error rates by an order of magnitude, but also reduces the number of undetected errors considerably. This work shows the importance of scheduling in the performance of iterative decoding algorithms and suggests that a schedule which matches the structure of the TG can substantially improve the performance/complexity trade-off in the decoding of short LDPC codes.

The joint Viterbi detector/decoder (JVDD) has been proposed as an alternative to the powerful and ubiquitous low-density parity check (LDPC) coding schemes, that are used in the majority of channel coding applications today. At shorter block lengths, the JVDD is able to outperform the state-of-the-art LDPC decoder that can be found in many of today’s systems, from deep-space communications to the digital video broadcasting standard, to the advanced television standard committee 3.0. Researchers have developed the tools to analyze the performance of the LDPC decoder, which is known as the sum-product algorithm or message passing algorithm. These tools include density evolution (DE) and extrinsic information transfer (EXIT) charts. To date, no similar such analysis exists for the JVDD. In the current paper we perform a similar preliminary analysis on the JVDD algorithm akin to what DE and EXIT charts are for the LDPC decoder. The current new analysis of the JVDD allows prediction of its probability of error based on the probability distribution functions of the metrics used within the algorithm. Our analysis plays a similar role to the abovementioned tools developed for the LDPC decoder: it allows us to predict the performance of the JVDD under various conditions (such as varying SNR’s, thresholds, and block lengths), it improves our understanding of the JVDD algorithm and the match against Monte-Carlo simulations verifies our assumptions on the main error-causing mechanisms within the JVDD.

Low-density parity-check codes are one of the most common forward error-correction techniques used in many existing and perspective standards including 5G wireless transmission standards and ultra-high-rate (400 Gbit/s and more) fiber-optic transmission standards. These codes should combine scalability of codelength from dozens to dozens of thousands bits and of coderate from low to very high with outstanding error-correcting performance when operating under severe practical limitations both from the point of view of decoding error and complexity issues. In many practical cases most widely used decoders suffer either from complexity out of system restrictions or from error performance penalties. In this paper the performance-complexity trade-off approach is considered, based on improved hard-decision decoders. Decoding of low-density parity-check codes with bit-flip algorithm is considered. The multi-threshold decoder based on the bit inversion algorithm is described using dynamically changed threshold during the decoding iterations, as well as the simplest empirical method is proposed for thresholds calculation. Simulation results in Gaussian channel with hard decision demodulation are given.

Conditional upper bounds are given for min-sum decoding of low-density parity-check codes in the error floor region. It is generally thought that absorbing sets, i.e., small collections of variable nodes connected to a relatively small number of unsatisfied check nodes, are the primary source of errors in the error floor region. The conditional upper bounds presented here are based on the assumption that all error floor errors are caused by absorbing sets. In order to bound the probability of error associated with each absorbing set, a directed-edge Tanner graph is used to link absorbing sets to low-weight deviations. These low-weight deviations result when a proportionally large number of nodes within a stopping set belong to an absorbing set contained inside the stopping set. A complete collection of the most problematic absorbing sets, and the minimum deviation weights that result from them, are used to derive a conditional upper bound on the probability of error for min-sum decoding of low-density parity-check codes. Simulation results are given to demonstrate the accuracy of the bound.

Belief-propagation (BP) decoders play a vital role in modern coding theory, but they are not suitable to decode quantum error-correcting codes because of a unique quantum feature called error degeneracy. Inspired by an exact mapping between BP and deep neural networks, we train neural BP decoders for quantum low-density parity-check codes with a loss function tailored to error degeneracy. Training substantially improves the performance of BP decoders for all families of codes we tested and may solve the degeneracy problem which plagues the decoding of quantum low-density parity-check codes.