Lowering the error floor of ADMM penalized decoder for LDPC codes

The alternating direction method of multipliers (ADMM) with over-relaxation and the accelerated ADMM are two effective methods to improve the convergence rate of ADMM. In this paper, an efficient linear programming (LP) decoder based on accelerated ADMM for low-density parity-check (LDPC) codes is proposed. Then it is shown that the ADMM update steps for decoding LDPC codes using the accelerated ADMM and the over-relaxed ADMM are quite similar. Therefore, it is impossible to obtain a more efficient ADMM decoder by combining the two improved ADMM methods. Simulation results also validate that the average number of iterations for LDPC decoding using the accelerated ADMM and the over-relaxed ADMM are close to each other.

The problem of low-complexity linear programming (LP) decoding of nonbinary low-density parity-check (LDPC) codes is considered, and an iterative LP decoding algorithm is presented. Results that were previously derived for binary LDPC codes are extended to the nonbinary case. Both simple and generalized nonbinary LDPC codes are considered. It is shown how the algorithm can be implemented efficiently using a finite-field fast Fourier transform. Then, the convergence rate of the algorithm is analyzed. The complexity of the algorithm scales linearly in the block length, and it can approximate, up to an arbitrarily small relative error, the objective function of the exact LP solution. When applied to a typical code from an appropriate nonbinary LDPC code ensemble, the algorithm can correct a constant fraction of errors in linear (in the block length) computational complexity. Computer experiments with the new iterative LP decoding algorithm show that, in the error floor region, it can have better performance compared to belief propagation decoding, with similar computational requirements.

Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.

The linear programming (LP) decoding of Low-Density Parity-Check (LDPC) codes is widely concerned for its maximum likelihood (ML) features. It is that the ML decoding rule for LDPC codes can be relaxed to LP optimization problem. Therefore, this paper focus on an efficient algorithm called infeasible primal-dual interior-point (IPDIP) to solve the LP problem. In each iteration, the IPDIP algorithm obtains the predictor and corrector steps by solving the Karush-Kuhn-Tucker (KKT) equation twice. The predictor term is used to responsible for optimal solution and the corrector term keeps the current iteration away from the boundary of the feasible region. Furthermore, a modification of the centering parameter is developed to accelerate the convergence speed for the IPDIP algorithm. Simulation results of LP decoding demonstrate that the proposed IPDIP algorithm achieves beautiful bit error rate (BER) performance and good global convergence properties with less iteration number and time than other algorithms which only solve the KKT equation once by Newton method or use the not modified centering parameter.

Error-correction codes (ECC) or channel codes allow correcting errors in a data sequence without the need to refer to the original source of information. By allowing reliable data transmission and storage despite the inevitable noise that perturbs physical signals, they dramatically reduce the cost of computer systems, and as such play a central role in enabling the digital revolution that we witness today. However, the decoding of channel codes often represents a significant part of the latency and energy consumption of a receiver. In this chapter, we review methods that can reduce the implementation complexity of ECC decoders by relying on stochastic computing. We focus on an important type of code called low-density parity-check (LDPC) codes, which are capacity-approaching codes that can be decoded using message-passing algorithms. These algorithms are inherently parallel, making LDPC codes attractive for simultaneously achieving a large coding gain and a high data throughput. In addition, we show that the use of stochastic computing is not limited to binary LDPC codes by describing a stochastic-computing decoder for non-binary LDPC codes, and another for Turbo codes.

Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their superior performance, especially at low Signal-to-Noise Ratio (SNR) such as are common in Powerline channels. For example, IEEE 1901-FFT PHY used the Turbo coding scheme defined in the HomePlug AV standards. However, patent fees are usually required for each turbo-code enabled manufactured device. The objective of this paper is to examine whether unlicensed LDPC codes, with optimized choices of block lengths, could be a viable alternative for future Powerline Communications (PLC) applications. The paper shows that the performance of the LDPC codes can approximate that of the Turbo codes with higher block lengths, on channels with typical and realistic PLC characteristics. The paper also shows that the additional complexity associated with this increase in block length can be mitigated by the use of Quasi-Cyclic LDPC (QC-LDPC) codes.

Low Density Parity Check (LDPC) codes have capacity-approaching performance over several channels of interest. In practice, for good block-error rate performance, the girth of the Tanner graph of an LDPC code needs to be as high as possible. In theory, to show that block-error rate approaches zero for increasing block-lengths, the girth of the Tanner graph sequence needs to tend to infinity with block-length. To meet these requirements, we construct sequences of large-girth irregular LDPC codes for a given degree-distribution pair (DDP) by applying a general node splitting algorithm on large girth graphs. The obtained Tanner graph meets the required DDP up to a suitable approximation. By optimizing the node-splitting method and using suitable large-girth graphs, we show code constructions with smaller block length for the same girth, when compared to previous constructions. Similar gains in block length are observed in the construction of sequences of large-girth protograph LDPC codes. Simulations, over a binary erasure channel, confirm the gains in block-error rate obtained by the large girth construction.

Big data storage demands larger cluster. The increasing size of the cluster may lead to failures of larger number of nodes. To provide reliable big data storage, replications are not cost-effective and does not provide a robust solution to prevent data loss. Traditional erasure codes applied in the RAID system such as Reed-Solomon (R-S) based solutions have limitations in providing high reliability. This is because higher reliability requires erasure codes with larger size. The computational cost of the R-S codes increase quadratically with the number of failures the R-S codes can tolerate for the same redundancy rate. It has been shown that Low Density Parity Check (LDPC) codes have lower computational cost and repair network traffic compared with R-S based solutions. Unfortunately, there does not exist a construction method for LDPC codes with larger size to control the computational cost and repair traffic. In this paper, a novel method is proposed to construct a family of LDPC codes - expanCodes with expandable sizes. The proposed expanCodes allows the encoding and decoding complexity remain unchanged with the increase of the size of the LDPC codes. As a result, increased reliability can be achieved without additional computation and repair traffic. The proposed expanCodes is integrated with the Hadoop system. Simulations show that more than 29% decrease in terms of encoding and decoding latency compared with R-S based solutions.

PMD mitigation through interleaving LDPC codes with polarization scramblers

<div> <h2>Abstract</h2> <p><strong>Objective:</strong> In the code theory, parallel concatenation of codes becomes more popular after the introduction of turbo codes. In recent years, the Low Density Parity Check (LDPC) code has found remarkable advancement and has seen them outshine turbo codes in terms of performance especially in the error floor and higher code rate. The main objective of this paper is to address the various techniques of a parallel concatenation of LDPC code in code theory. <strong>Method/Finding:</strong> To reduce the complexity of encoding and decoding for longer codes various parallel concatenation of LDPC coding methods were introduced and the performance was compared with other work. <strong>Novelty:</strong> When a longer block length is used, the parallel LDPC decoder is suffered from the complexity of prohibitive implementation. To overcome this issue and to achieve the best performance for longer codes, the different methods for parallel concatenation of LDPC codes were introduced with reduced complexity. This will helps to break the long and complex LDPC code into less complex and smaller LDPC to distribute the decoding and encoding load. Also, this will provides scalability and scope for improving the performance of LDPC codes in practical delay-sensitive and energy-aware applications.</p> <p><strong>Keywords:</strong> Parallel concatenation; LowDensity ParityCheck (LDPC); turbo codes; Parallel Concatenated Gallager Codes (PCGC)</p> </div> <div></div> <div> </div>

For low-density parity-check (LDPC) codes decoding by alternating direction method of multipliers (ADMM), the layered scheduling sequentially updates the messages of check nodes one by one. Though the layered scheduling can speed up the convergence rates, it may limit the throughput when implementing the ADMM decoder with multi-core systems due to its serial style. To circumvent this problem, a group-based layered scheduling is proposed by updating a group of check node messages at one time. Extensive simulation results for the proposed scheme over two typical LDPC codes with the ADMM penalized decoding algorithm are provided.

We propose a novel concatenated coding scheme combined Low Density Parity Check(LDPC) code and vertical Bell Labs layered space-time (VBLAST) code to improve the bit error rate (BER) performance for Free-space optical (FSO) communication links with On Off Keying(OOK) modulation. In the scheme, π-rotation encoding and belief-propagation (BP) decoding algorithm are employed in LDPC code, and minimum mean-square error (MMSE) soft-decision decoding algorithm is used for VBLAST code. Moreover, a joint iterative detection and decoding algorithm of VBLAST code and LDPC code is used to improve the overall link performance. At last, the BER of the proposed scheme over lognormal atmospheric turbulent fading channels is analyzed by using Monte Carlo method. The result shows that the BER of the proposed concatenated coding scheme is much improved than that only use VBLAST code scheme.

Four new messages for decoding of low-density parity-check (LDPC) codes are proposed. An a posteriori probability ratio (APPR) message, an a posteriori probability (APP) message, and an a posteriori probability difference (APPD) message for variable and check nodes are derived for sum-product decoding of LDPC codes. Also, we propose a hybrid APPD-APPR message, which denotes a hybrid message with an APPD variable node message and APPR check node message. All the proposed messages require only addition, subtraction, multiplication, and division operations for decoding of LDPC codes. We show that the hybrid APPD-APPR message-passing has the lowest complexity among the proposed messages.

Low-density Parity check codes (LDPC) are gaining interest for high data rate application in both terrestrial and spatial communications which requires low bit error rate. This paper proposes an algorithm through which the best parity check matrix is obtained for irregular low density parity check codes, which reduces the Bit Error Rate ,Frame Error Rate and computational complexity. Tanner graph also called a bipartite graph format in an Low Density Parity Check (LDPC) code design contains many short cycles; it will produce a computational complexity in a code design process and it degrades the code performance. To overcome this effect, we proposed an new algorithm which obtains a best final parity check matrix. Throughout the paper we will give the detailed description of an efficient algorithm proposed. The complexity is studied graphically and analytically. Using proposed algorithm, cycles of length four observed in corresponding matrix are removed. Each matrix is evaluated over a noisy Additive White Gaussian Noise (AWGN) channel. Bit Error rate and Frame error rate is calculated. The results are compared with randomly generated best parity check matrix. Simulation results shows that proposed method successfully overcomes the computational complexity and meets the near Shannon limit.

This letter gives a random construction for Low Density Parity Check (LDPC) codes, which uses an iterative algorithm to avoid short cycles in the Tanner graph. The construction method has great flexible choice in LDPC code’s parameters including codelength, code rate, the least girth of the graph, the weight of column and row in the parity check matrix. The method can be applied to the irregular LDPC codes and strict regular LDPC codes. Systemic codes have many applications in digital communication, so this letter proposes a construction of the generator matrix of systemic LDPC codes from the parity check matrix. Simulations show that the method performs well with iterative decoding.