Stochastic Decoding of Error-Correcting Codes

Big data storage demands larger cluster. The increasing size of the cluster may lead to failures of larger number of nodes. To provide reliable big data storage, replications are not cost-effective and does not provide a robust solution to prevent data loss. Traditional erasure codes applied in the RAID system such as Reed-Solomon (R-S) based solutions have limitations in providing high reliability. This is because higher reliability requires erasure codes with larger size. The computational cost of the R-S codes increase quadratically with the number of failures the R-S codes can tolerate for the same redundancy rate. It has been shown that Low Density Parity Check (LDPC) codes have lower computational cost and repair network traffic compared with R-S based solutions. Unfortunately, there does not exist a construction method for LDPC codes with larger size to control the computational cost and repair traffic. In this paper, a novel method is proposed to construct a family of LDPC codes - expanCodes with expandable sizes. The proposed expanCodes allows the encoding and decoding complexity remain unchanged with the increase of the size of the LDPC codes. As a result, increased reliability can be achieved without additional computation and repair traffic. The proposed expanCodes is integrated with the Hadoop system. Simulations show that more than 29% decrease in terms of encoding and decoding latency compared with R-S based solutions.

Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their superior performance, especially at low Signal-to-Noise Ratio (SNR) such as are common in Powerline channels. For example, IEEE 1901-FFT PHY used the Turbo coding scheme defined in the HomePlug AV standards. However, patent fees are usually required for each turbo-code enabled manufactured device. The objective of this paper is to examine whether unlicensed LDPC codes, with optimized choices of block lengths, could be a viable alternative for future Powerline Communications (PLC) applications. The paper shows that the performance of the LDPC codes can approximate that of the Turbo codes with higher block lengths, on channels with typical and realistic PLC characteristics. The paper also shows that the additional complexity associated with this increase in block length can be mitigated by the use of Quasi-Cyclic LDPC (QC-LDPC) codes.

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

Decoding by alternating direction method of multipliers (ADMM) is a promising linear programming decoder for low-density parity-check (LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder. For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.

Terrestrial digital multimedia TV/handle broadcasting (DMB-TH) is a newly upcoming framing structure, channel coding and modulation for digital television terrestrial broadcasting system standard of China, which is recently drafted and is ready to be verified in order to deploy mobile multimedia broadcasting services for the public. The adoption of strong channel coding techniques appears to be of key importance for mobile operators and broadcasters. Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presents a turbo-decoding message-passing algorithm (TDMP) based LDPC code search algorithm with hardware considerations. The main advantages of the proposed algorithm over the DMB-TH standard decoding algorithm are 1) improvement in coding gain by an order of magnitude at high signal-to-noise ratio (SNR), 2) reduced decoder complexity. The performance of the proposed TDMP architecture is shown by the comparison of simulation results.

In communication systems, the transmitted data is corrupted by channel perturbations, such as noise and fading, which affect the reliability of the received data. Error correction codes are employed to mitigate channel perturbations. However, design and implementation of good and efficient error correction codes remains an open problem. In this paper, Low Density Parity Check (LDPC) codes are considered as they provide a reasonable trade-off between computational complexity and reliability. Good LDPC codes should ideally provide low complexity, close to capacity acheivable transmission rate, high coding threshold, and high decoding stability. In this paper, we investigate a joint LDPC code optimization algorithm using Genetic Algorithm (GA) and Linear Programming (LP) to determine the variable nodes and check nodes degrees distributions. EXIT chart analysis and Frame Error Rate (FER) performance are used to validate the proposed method.

Low Density Parity Check (LDPC) codes have capacity-approaching performance over several channels of interest. In practice, for good block-error rate performance, the girth of the Tanner graph of an LDPC code needs to be as high as possible. In theory, to show that block-error rate approaches zero for increasing block-lengths, the girth of the Tanner graph sequence needs to tend to infinity with block-length. To meet these requirements, we construct sequences of large-girth irregular LDPC codes for a given degree-distribution pair (DDP) by applying a general node splitting algorithm on large girth graphs. The obtained Tanner graph meets the required DDP up to a suitable approximation. By optimizing the node-splitting method and using suitable large-girth graphs, we show code constructions with smaller block length for the same girth, when compared to previous constructions. Similar gains in block length are observed in the construction of sequences of large-girth protograph LDPC codes. Simulations, over a binary erasure channel, confirm the gains in block-error rate obtained by the large girth construction.

Cooperative diversity or user cooperation achieves the diversity gain without adding physical antennas to the users or mobile stations. The users work in cooperative fashion using their single antennas to create a virtual transmit diversity, called relay diversity or cooperative diversity. The diversity gain achieved by cooperative diversity can be further improved using error correction codes. Low-density parity-check (LDPC) codes are linear block codes with good error correction capabilities. We present a novel approach using extended LDPC codes to increase the diversity gain in cooperative diversity. We also compare the extended LDPC codes with punctured LDPC codes in cooperative diversity and show that extended LDPC codes have lesser complexity than punctured LDPC codes in cooperative diversity.

We propose a novel concatenated coding scheme combined Low Density Parity Check(LDPC) code and vertical Bell Labs layered space-time (VBLAST) code to improve the bit error rate (BER) performance for Free-space optical (FSO) communication links with On Off Keying(OOK) modulation. In the scheme, π-rotation encoding and belief-propagation (BP) decoding algorithm are employed in LDPC code, and minimum mean-square error (MMSE) soft-decision decoding algorithm is used for VBLAST code. Moreover, a joint iterative detection and decoding algorithm of VBLAST code and LDPC code is used to improve the overall link performance. At last, the BER of the proposed scheme over lognormal atmospheric turbulent fading channels is analyzed by using Monte Carlo method. The result shows that the BER of the proposed concatenated coding scheme is much improved than that only use VBLAST code scheme.

Scheduling strategy is considered an important aspect of belief-propagation (BP) decoding of low-density parity-check (LDPC) codes because it affects the decoder's convergence rate, decoding complexity and error-correction performance. In this paper, we propose two new scheduling strategies for the BP decoding of non-binary LDPC (NB-LDPC) codes. Both the strategies are devised based on the concept of check node reliability and employ a heuristically defined threshold which can adapt to the communication channel variations. As the scheduling strategies only update a subset of the check nodes in each iteration, they result in reduced iteration cost. Furthermore, since the BP performs suboptimally for finite-length LDPC codes, especially for short-length LDPC codes, by enhancing the message propagation over the Tanner Graphs of short-length NB-LDPC codes, the new scheduling strategies can even improve the error-correction performances of BP decoding. Simulation results demonstrate that the new scheduling strategies provide good performance/complexity tradeoffs.

This letter gives a random construction for Low Density Parity Check (LDPC) codes, which uses an iterative algorithm to avoid short cycles in the Tanner graph. The construction method has great flexible choice in LDPC code’s parameters including codelength, code rate, the least girth of the graph, the weight of column and row in the parity check matrix. The method can be applied to the irregular LDPC codes and strict regular LDPC codes. Systemic codes have many applications in digital communication, so this letter proposes a construction of the generator matrix of systemic LDPC codes from the parity check matrix. Simulations show that the method performs well with iterative decoding.

DOI: 10.1049/cp:20061337 ISBN: 0 86341 644 6 Location: Hangzhou, China Conference date: 6-9 Nov. 2006 Format: PDF The BER performance of presented quasi-cyclic (QC) low-density parity-check (LDPC) codes is not good as that of randomly constructed LDPC codes, while the lack of structure of randomly constructed LDPC codes implies serious disadvantages in terms of storing and accessing a large parity-check matrix. To solve the problems, this paper proposes a design of good quasi-cyclic (QC) low-density parity-check (LDPC) codes, the obtained algebraically structured codes have large minimum distances and good BER performance. The proposed design is based on index matrices, which determines the shifts of the circulant matrices of the sparse parity-check matrices. Compared with the presented design of QC LDPC codes, the designed QC LDPC codes are free from girth 4, sometimes free from girth 6, and have much larger minimum distances. Based on the algebraic code structure, the conditions of the girth and minimum distance of the codes are found. The BER performance of the designed QC LDPC block codes compares with that of randomly constructed LDPC codes for any block lengths. Better BER performance is obtained by increasing the circulant size of the base QC code. Simulations verify the construction of the QC LDPC codes to be valid. (4 pages) Inspec keywords: AWGN channels; error statistics; channel coding; algebraic codes; parity check codes; sparse matrices Subjects: Algebra; Other topics in statistics; Codes

PMD mitigation through interleaving LDPC codes with polarization scramblers

Low Density Parity Check (LDPC) codes are Shannon-Limit approaching codes. Shannon stated the theoretical bounds for digital data transmission in a given channel capacity with error correction coding. Spread Spectrum also called as CDMA (Code Division Multiple Access) is an efficient way of radio wave communication deployed in commercial broadcasts, ham radios, military communications, police radios, etc. CDMA is a means of signal transmission in which the signal frequency is spread over a very wide bandwidth. Spreading of data is achieved prior to transmission with the help of an independent code called ‘Pseudo Noise Code’ (PN sequences), which is subsequently used in the receiver end to de-spread the signal received in order to recover the signal data. PN sequences based on prime numbers like Legendre & Weil sequences are used in the present work. An impressive part of LDPC lies in its decoding algorithm. Sum-Product Algorithm (SPA) decoding offers the best error performance amongst all the types of decoding techniques of LDPC codes and thus applied here. This paper demonstrates an idea of introducing LDPC codes along with DS-Spread Spectrum technique using Legendre & Weil sequences. In the present work, the encoding and decoding algorithms are applied after spreading of the signal. SPA decoding technique is successfully employed and simulated results are plotted taking an example design to illustrate the concepts discussed above.

The linear programming (LP) decoding of Low-Density Parity-Check (LDPC) codes is widely concerned for its maximum likelihood (ML) features. It is that the ML decoding rule for LDPC codes can be relaxed to LP optimization problem. Therefore, this paper focus on an efficient algorithm called infeasible primal-dual interior-point (IPDIP) to solve the LP problem. In each iteration, the IPDIP algorithm obtains the predictor and corrector steps by solving the Karush-Kuhn-Tucker (KKT) equation twice. The predictor term is used to responsible for optimal solution and the corrector term keeps the current iteration away from the boundary of the feasible region. Furthermore, a modification of the centering parameter is developed to accelerate the convergence speed for the IPDIP algorithm. Simulation results of LP decoding demonstrate that the proposed IPDIP algorithm achieves beautiful bit error rate (BER) performance and good global convergence properties with less iteration number and time than other algorithms which only solve the KKT equation once by Newton method or use the not modified centering parameter.