Joint code-encoder-decoder design for LDPC coding system VLSI implementation

In previous works, density evolution schemes have been used to design an irregular low-density parity-check (LDPC) code for the multi-input multi-output (MIMO) systems. However the code design based on the density evolution can be used only for simple code structure like LDPC codes and repeat-accumulate (RA) codes. Recently simple and accurate irregular LDPC code design method based on the extrinsic information transfer (EXIT) chart was introduced for an AWGN channel. This code design scheme is much flexible, therefore it can be used for any kind of code structure like turbo codes. In this paper we design an irregular LDPC code for a MIMO system using the EXIT chart based scheme. The EXIT charts are used to obtain the optimal edge degree distribution of the irregular LDPC code combined with the MMSE-SIC MIMO detector. This scheme can be generalized for designing the optimal iterative MIMO detector combined with any kind of channel codes including turbo codes.

Low Density Parity Check (LDPC) codes have capacity-approaching performance over several channels of interest. In practice, for good block-error rate performance, the girth of the Tanner graph of an LDPC code needs to be as high as possible. In theory, to show that block-error rate approaches zero for increasing block-lengths, the girth of the Tanner graph sequence needs to tend to infinity with block-length. To meet these requirements, we construct sequences of large-girth irregular LDPC codes for a given degree-distribution pair (DDP) by applying a general node splitting algorithm on large girth graphs. The obtained Tanner graph meets the required DDP up to a suitable approximation. By optimizing the node-splitting method and using suitable large-girth graphs, we show code constructions with smaller block length for the same girth, when compared to previous constructions. Similar gains in block length are observed in the construction of sequences of large-girth protograph LDPC codes. Simulations, over a binary erasure channel, confirm the gains in block-error rate obtained by the large girth construction.

In mobile communications, the quality of signal is deteriorated by fading. The spatial diversity technique is used to reduce the degradation of the signal by fading. There are several techniques to realize the spatial diversity gain, such as Single- Input Multiple-Output (SIMO), Space-Time Block Code (STBC), and so on. The SIMO system realizes the receive diversity. The error correcting code can be combined with spatial diversity gain. Low-Density Parity Check (LDPC) codes can achieve good performance approaching Shannon limit. In particular, an irregular LDPC code with optimum degree distribution achieves better performance than a regular LDPC code. The optimum degree distribution of the irregular LDPC code depends both on the channel and the system. In this paper, we derive the Eb/No thresholds of a regular LDPC codes and the irregular LDPC codes for SIMO systems with several diversity orders. The Eb/No threshold is the smallest Eb/No that the decoder can achieve the error free. We also derive the optimum degree distributions of the irregular LDPC codes for SIMO systems with several diversity orders. We show that with low diversity order, the optimum degree distributions of the irregular LDPC code depends on the diversity order largely, while with high diversity order, the optimum degree distribution depends both on the diversity order and the combining scheme largely. We also show that comparing the optimum degree distributions for MRC and STBC, when the diversity orders are the same, the optimum degree distributions are also the same.

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

In order to improve the security level of the physical layer, a new encryption scheme based on the irregular low-density parity-check (LDPC) codes is proposed in this paper. The degree distribution property of the irregular LDPC codes and a large random number are applied to encrypt the plaintext. Analyses show that the proposed scheme can provide an acceptable security level for the communication systems. The secret key size of this scheme is much smaller than those of the previous symmetric-key McEliece-like schemes. Moreover, there is no trade-off between the error correction performance and the security level in the proposed scheme.

In this letter, we obtain lower and upper bounds on the minimum distance $d_{\min }$ of low-density parity-check (LDPC) codes. The bounds are derived by categorizing the non-zero code words of an LDPC code into two categories of elementary and non-elementary. The first category contains code words whose induced subgraph has only degree-2 check nodes. We propose an efficient search algorithm that can find the elementary code words of an LDPC code with weight less than a certain value $a_{\max }$ , exhaustively. We also derive a lower bound $L_{ne}$ on the weight of non-elementary code words. By performing the search with $a_{\max } = L_{ne}$ , we either obtain an elementary code word with the smallest weight $d_{\min }$ , or establish the lower bound of $L_{ne}$ on $d_{\min }$ . For the upper bound, we modify our search algorithm to reach elementary codewords of larger weights at the cost of being non-exhaustive. Once such a codeword is found, its weight acts as an upper bound on $d_{\min }$ . We examine a large number of regular and irregular LDPC codes, and demonstrate the efficiency and versatility of our technique in finding lower and upper bounds on, and in many cases the exact value of, $d_{\min }$ . Finding $d_{\min }$ , or establishing search-based lower or upper bounds, for many of the examined codes are out of the reach of any existing algorithm.

In order to solve high encoding complexities of irregular low-density parity-check (LDPC) codes, a deterministic construction of irregular LDPC codes with low encoding complexities was proposed. And the encoding algorithms were designed, whose complexities are linear equations of code length. The construction and encoding algorithms were derived from the effectively encoding characteristics of repeat-accumulate (RA) codes and masking technique. Firstly, the new construction modified parity-check matrices of RA codes to eliminate error floors of RA codes. Secondly, the new constructed parity-check matrices were based on Vandermonde matrices, this deterministic algebraic structure was easy for hardware implementation. Theoretic analysis and experimental results show that, at a bit-error rate of 10×10−4, the new codes with lower encoding complexities outperform Mackay’s random LDPC codes by 0.4–0.6 dB over an additive white Gauss noise (AWGN) channel.

In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partially parallel LDPC architecture is commonly used for reducing the area cost of the processing units. The dependency of two kinds of processing units, check node unit (CNU) and bit node unit (BNU), should be considered to enhance the hardware utilization efficiency (HUE). Based on the properties of the parity check matrix of LDPC codes, the updating calculation of the CNU and BNU can be overlapped to reduce the decoding latency by enhancing the HUE with the matrix scheduling algorithm. By applying our proposed LDPC scheduling algorithm to a (1944, 972)-irregular LDPC code, we can get about 60% throughput gain in average without any performance degradation.

Low Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means its actual building exists that enables outer edge to be closely intended for symmetry of a channel with no memory. FPGA or Field Programmable Gate Array is based on configurable logic block (CLB) and is a semiconductor gadget that is associated by virtue of programmable interconnects. FPGAs are highly robust and can be created or designed as per the application or usefulness prerequisite of application. This research paper presents adaptable and more compatible LDPC decoder in change for other general LDPC decoder. This decoder has a completely adaptable LDPC plan in FPGA, which supports distinct codes and rate of information. The design is implemented in Xilinx ISE 14.2 software using VHDL programming and synthesized on SPARTAN 3E FPGA. Keywords: Sparse bipartite graph, threshold, Shannon limit, Very High Speed Integrated Circuit Hardware Description Language (VHDL) Cite this Article Sachit Gupta, Richa, Adesh Kumar. FPGA Implementation of LDPC Codes. Journal of Telecommunication, Switching Systems and Networks . 2018; 5(1): 21–28p.

In this paper, we propose a concatenated code by combining a Recursive Systematic Convolutional (RSC) code with a Low-Density Parity-Check (LDPC) code. The proposed concatenated code is encoded in parallel by an RSC encoder and an LDPC encoder without interleavers between them. When decoding the proposed concatenated code, the information bits are decoded by two decoding algorithms, and soft information is exchanged between the RSC decoder and the LDPC decoder. This allows for the elimination of wrong codewords output by each decoder. The use of an LDPC code allows us to halt the decoding process when the valid codeword is obtained. We evaluate the error rate performance of the proposed concatenated code by computer simulations. We show that the proposed concatenated code does not have a high error floor, and achieves better BLock Error Rate (BLER) performance than either conventional LDPC codes or conventional turbo codes in the high Eb/No region. We also show that since the proposed concatenated code can correct wrong codewords output by each decoder, it achieves better BLER than the regular LDPC code at the same Bit Error Rate (BER).

This paper investigates the detection schemes for single-carrier underwater acoustic communications over the severe time-dispersive channels. A low-density parity-check (LDPC) code is employed for the improvement of the equalization performance. A detection scheme with Turbo conception is proposed which includes a LDPC decoder in the feedback loop of an iterative block decision feedback equalizer (IB-DFE), combining the iterative frequency domain equalization of IB-DFE with the iterative LDPC decoding. The external messages are fully exchanged between the IB-DFE and the decoder during the processing of the joint iterative equalization and decoding. The numerical results demonstrate that the decision signals with higher reliability from the LDPC decoder accelerate the convergence of the equalizer and enhance the detection performance, yielding up to 6 dB performance gains when compared with the scheme without LDPC code. Compared with the concatenated scheme in which the process of the iterative frequency domain equalization is serial concatenated with that of the iterative LDPC decoding, the combined scheme obtains about 2 dB performance gains.

DOI: 10.1049/cp:20061337 ISBN: 0 86341 644 6 Location: Hangzhou, China Conference date: 6-9 Nov. 2006 Format: PDF The BER performance of presented quasi-cyclic (QC) low-density parity-check (LDPC) codes is not good as that of randomly constructed LDPC codes, while the lack of structure of randomly constructed LDPC codes implies serious disadvantages in terms of storing and accessing a large parity-check matrix. To solve the problems, this paper proposes a design of good quasi-cyclic (QC) low-density parity-check (LDPC) codes, the obtained algebraically structured codes have large minimum distances and good BER performance. The proposed design is based on index matrices, which determines the shifts of the circulant matrices of the sparse parity-check matrices. Compared with the presented design of QC LDPC codes, the designed QC LDPC codes are free from girth 4, sometimes free from girth 6, and have much larger minimum distances. Based on the algebraic code structure, the conditions of the girth and minimum distance of the codes are found. The BER performance of the designed QC LDPC block codes compares with that of randomly constructed LDPC codes for any block lengths. Better BER performance is obtained by increasing the circulant size of the base QC code. Simulations verify the construction of the QC LDPC codes to be valid. (4 pages) Inspec keywords: AWGN channels; error statistics; channel coding; algebraic codes; parity check codes; sparse matrices Subjects: Algebra; Other topics in statistics; Codes

Summary form only given. The ultimate performance limit or threshold of low-density parity-check (LDPC) codes is close to capacity over various memoryless channels (S.-Y. Chung, IEEE Trans. Info. Theory, vol. 47, pp. 657-670, 2001). Since the capacity of binary-input partial response (PR) channels is unknown, we estimate the capacity by calculating the threshold of capacity-approaching LDPC codes over these channels. We assume a BCJR equalizer for the channel and a sum-product message-passing decoder for the LDPC code. We also assume that the log-likelihood ratios (LLRs) in the channel BCJR and the LDPC decoder are Gaussian. We use our results to guide the design of decoder schedules that minimize the number of computationally expensive BCJR steps. The threshold calculation method can be used to optimize the left and right degree sequences of the LDPC code factor graph, using fast linear programming methods, to provide better thresholds than regular codes.

The application of Low Density Parity Check (LDPC) code in the anti-interference systems has drawn an increasing attention, due to its admiring performance which is very close to the theory limit. This paper focuses on a LDPC encoded slow frequency hopping (SFH) communication system with partial-band interference. Firstly, a modified soft- decision algorithm based on the utilization of interference information is proposed, and its performance is compared with some other soft-decision methods. Secondly, with numerical simulation, the influence of code rate, code length and the number of symbols per hops on the performance of the system with partial band noise interference is illustrated and examined in detail. Considering the great influence of hops per symbol on the performance, interleaver should be used and its influence on the performance is further examined by simulation. Finally, some constructive advises for the design of LDPC coded SFH system are given. Simulation results show that, with a reasonable design, the SFH system with LDPC code could achieve a desirable performance.

In this paper, in order to improve bit error performance, bandwidth efficiency and reduction of complexity compared to related schemes such as turbo codes, we combine low density parity check (LDPC) codes and continuous phase frequency shift keying (CPFSK) modulation and introduce a new scheme, called ‘low density parity check coded‐continuous phase frequency shift keying (LDPCC‐CPFSK)’. Since LDPC codes have very large Euclidean distance and use iterative decoding algorithms, they have high error correcting capacity and have very close performances to Shannon limit. In all communication systems, phase discontinuities of modulated signals result extra bandwidth requirements. Continuous phase modulation (CPM) is a powerful solution for this problem. Beside CPM provides good bandwidth efficiency; it also improves bit error performance with its memory unit. In our proposed scheme, LDPC and CPFSK, which is a special type of CPM, are considered together to improve both error performance and bandwidth efficiencies. We also obtain error performance curves of LDPCC‐CPFSK via computer simulations for both regular and irregular LDPC code. Simulation results are drawn for 4‐ary CPFSK, 8‐ary CPFSK and 16‐ary CPFSK over AWGN, Rician and Rayleigh fading channels for maximum 100 iterations, while the frame size is chosen as 504. Copyright © 2006 John Wiley & Sons, Ltd.