Joint Network-Source Video Coding Based on Lagrangian Rate Allocation

Video communication requires sufficient resources to obtain the desired image quality. Availability of bandwidth and screen resolution from different devices on the client end, as well as compression techniques used for transmission also significantly influence to the video quality. Even though the H.264/AVC video compression standard and its scalable extension is known as Scalable Video Coding (SVC) was introduced and successfully addressed the challenge, some weaknesses persist especially for high-resolution video transmissions. The size of the bitstream generated by the SVC standard for ultra-high resolution video compression can only be met if transmitted on a network with a large bandwidth. The Scalable High-Efficiency Video Coding (SHVC) were introduced to overcome problems in the SVC standards. The new video compression standard is proven to reduce bandwidth requirements by up to 46.41 % compared to the SVC standards for the same video quality. This study introduces the performance analysis of SHVC standard video transmission as compared to SVC standard. Both compression standards are transmitted and emulated through network emulator called Mininet-Wifi to get the real transmission picture. The client-server video transmission scheme with different bandwidth and various client position are set in the experiment scenario. It is found that transmission time, packet loss, and video reconstruction quality on scalable video transmission with SHVC standard is better than scalable video transmissions with SVC standard.

Context-based adaptive binary arithmetic coding (CABAC) is a single entropy coding mode of the newest video coding standard, High Efficiency Video Coding (HEVC). Despite the high coding efficiency of CABAC, its data dependencies prevent effective parallelization, which also means limited throughput. Accordingly, during the HEVC standardization activity of entropy coding, both coding efficiency and throughput were considered. This paper highlights the key techniques that were proposed and adopted up to HEVC Draft International Standard (DIS). In addition, a new method is proposed for high throughput entropy coding. This method reduces the worst-case complexity of entropy coding without significant coding efficiency loss. From the experimental results, in terms of throughput improvement, we confirm that the proposed method reduces the number of context-coded bins up to 42.1 and 15.9 % on average.

Hardware implementation of HEVC CABAC binarization/de-binarization

This paper uses joint algorithm and architecture design to enable high coding efficiency in conjunction with high processing speed and low area cost. Specifically, it presents several optimizations that can be performed on Context Adaptive Binary Arithmetic Coding (CABAC), a form of entropy coding used in H.264/AVC, to achieve the throughput necessary for real-time low power high definition video coding. The combination of syntax element partitions and interleaved entropy slices, referred to as Massively Parallel CABAC, increases the number of binary symbols that can be processed in a cycle. Subinterval reordering is used to reduce the cycle time required to process each binary symbol. Under common conditions using the JM12.0 software, the Massively Parallel CABAC, increases the bins per cycle by 2.7 to 32.8× at a cost of 0.25 to 6.84% coding loss compared with sequential single slice H.264/AVC CABAC. It also provides a 2× reduction in area cost, and reduces memory bandwidth. Subinterval reordering reduces the critical path delay by 14 to 22%, while modifications to context selection reduces the memory requirement by 67%. This work demonstrates that accounting for implementation cost during video coding algorithms design can enable higher processing speed and reduce hardware cost, while still delivering high coding efficiency in the next generation video coding standard.

H.264/AVC offers critical advantages over other video compression schemes at the price of increased computational complexity. The efficiency of hardware video encoders depends on all modules embedded in the processing path. This paper presents the architecture of the H.264/AVC binary coder, which is the last stage of the video coder. The module conforms to H.264/AVC High Profile and supports two binary coding modes: context adaptive binary arithmetic coding (CABAC) and context adaptive variable-length coding (CAVLC). The architecture saves a considerable amount of hardware resources since two coding modes share the same logic and storage elements. Five versions of the arithmetic coding path are developed to study the area/performance tradeoff related to parallel symbol encoding. The implementation results show that the parallel symbol encoding allows higher efficiency. The whole architecture of the binary coder is described in VHDL and synthesized for different configurations to show the implementation cost of some coding options. For both CAVLC and CABAC modes, the architecture achieves the similar throughput able to support HDTV in real time.

Current digital video applications require delivery of digital video content to different clients over heterogeneous networks. These clients may have different system resources and bandwidth capabilities. Thus, delivering of digital video data compressed at specific spatial resolution, quality levels, frame rates and encoding those video data at specific bit rates according to the client resources and the available network is essential. The characteristics of current video transmission system pose many problems for video delivery and scalable video coding is a highly attractive solution. This thesis investigates the existing video coding standards, especially the newest H.264/advanced video coding and its scalable extension: scalable video coding. In this thesis, we address two issues related to the state-of-the-art scalable video coding: 1) computational complexity reduction; and 2) video coding efficiency enhancement. In the first part of this thesis, we address the complexity issue of spatial, signal-to-noise ratio (SNR), temporal and combined scalable video coding. Our goal is to find a good tradeoff between computational complexity and video coding efficiency. We first establish the need to reduce computational complexity for current H.264/advanced video coding and scalable video coding framework. We then evaluate the mode distribution correlations between the base layer and its enhancement layers for different video scalabilities. After the exhaustive search over all possible block partitions is performed at the base layer, the number of candidate modes for luma and chroma blocks in a macroblock that take part in rate distortion optimization calculation at enhancement layers could be greatly reduced based on the correlations. Finally, adaptive fast mode decision schemes for spatial, SNR and temporal scalable video coding are presented. Our schemes could achieve consistent and significant computational complexity reduction with negligible loss in objective and subjective video quality and insignificant increments in bit rate consumption. The second part of this thesis is to provide a solution for the problem of high computational complexity of scalable video decoders. An adaptive encoding algorithm is proposed to reduce decoder complexity in coarse grain SNR scalable video coding.

In this paper, we propose a selective encryption scheme with a chaotic encryption system for the High Efficiency Video Coding (HEVC) standard in which Context Adaptive Binary Arithmetic Coding (CABAC) is the only entropy coder for transform coefficient coding. Our method focuses on the binstrings of truncated rice with a context “p” (TRp) code suffix and kth order Exp-Golomb (k = p + 1) code suffix before Binary Arithmetic Coding (BAC) for the remaining absolute level coding, which is coded by the bypass mode in the entropy coding stage. The probability of symbols does not change and CABAC decoding has no effect after encryption. Several different YUV sequences are used for experimental evaluation of the proposed algorithm. Compared to previous researches, our approach has good protection for video information, which keeps a constant bitrate and format compatibility, and meantime it has a negligible impact on encoding performance.

The rate-distortion (R-D) optimized mode decision is very important to obtaining full benefit from various powerful coding tools in the most recent video coding standard, namely the high efficiency video coding (HEVC). In deciding a certain coding mode, the R-D optimality criterion takes into account both distortion and bit rate. The bit-rate is generally measured from the number of bits in the bitstream that context-adaptive binary arithmetic coding (CABAC) generates through performing a series of binarization, context modeling, interval subdivision, renormalization, outstanding bit handling, and context updating. Its simplification is important to reduce the high complexity of actual bit rate estimation by CABAC. This paper proposes the efficient estimation of output bits by counting only the number of generated binarized output of the binarization process in CABAC. The proposed method only executes binarization, without performing context modeling, interval subdivision renormalization, outstanding bit handling, or context updating. We evaluate the performances of the proposed method using HEVC reference software, and our experimental results verify that the proposed scheme is very effective in reducing the complexity of rate calculation. Compared to the HEVC reference software that performs all the CABAC execution steps, the proposed method shows an average saving in rate calculation time for all intra, low delay, and random access conditions of 55.29%, 41.05%, and 42.96%, respectively.

Multidimensional Signal, Image, and Video Processing and Coding

Ultra High Definition Television (UHDTV) imposes extremely high throughput requirement on video codec's based on High Efficiency Video Coding (H.265/HEVC). Context-based adaptive binary arithmetic coding (CABAC) is specified as the single operation mode for entropy coding in HEVC. Parallel and pipeline processing can be used to increase the throughput for higher performance and decrease the path delay. This paper proposes a pipeline and parallel CABAC decoder architecture adaptive to HEVC syntax elements, In order to reduce the critical path delay, we stored the RangeLps LUT and LZ LUT in the same memory and we exploit different techniques of optimization. The implementation can process 1,5 bins/cycle when operate at 133,31 MHz and improved high throughput of 200Mbin/s for parallel decoder and process 1.49 bins/cycle when operate at 134.2 MHz with throughput of 200Mbin/s for pipeline decoder. The critical path delay is optimized compared to the serial process and the architecture is coded using VHDL language, simulated and synthesized using Xilinx tools with virtex4 xc4vsx25-12ff668 card.

This paper presents a hardware design of context-based adaptive binary arithmetic coding (CABAC) for the emerging High efficiency video coding (HEVC) standard. While aiming at higher compression efficiency, the CABAC in HEVC also invests a lot of effort in the pursuit of parallelism and reducing hardware cost. Simulation results show that our design processes 1.18 bins per cycle on average. It can work at 357 MHz with 48.940K gates targeting 0.13 μm CMOS process. This processing rate can support real-time encoding for all sequences under common test conditions of HEVC standard conforming to the main profile level 6.1 of main tier or main profile level 5.1 of high tier.

In this paper, we present a comparative performance analysis of low power hardware architecture for real time implementation of context adaptive binary arithmetic coding algorithm and Context-based adaptive Variable Length Coding algorithm (CAVLC) used in H.264/ MPEG part 10 video coding standards. The video compression efficiency achieved in H.264 standard is not a result of any single feature but rather a combination of a number of encoding tools. CAVLC requires considerably more processing power to decode. The encoding process is simulated by MATLAB which compress the input video sequence and ensures better performance in video compression. The results that are obtained reveal better performance of both entropy coding methods.

The advanced video codec of H.264/AVC has been extensively employed for data compression for efficient video storage or transmissions. However, its intensive computational complexity causes a bottleneck for its real-time applications. Simultaneously, the sequential operation in the normal encoding process is not favorable with regard to hardware implementations. In this paper, a high-speed and accurate bit-rate estimation scheme is proposed to skip the actual entropy engine of context-adaptive binary arithmetic coding (CABAC), which is useful for reducing the computational complexity and saving the encoding time in H.264/AVC rate distortion (RD) optimization for mode decision. The characteristics of syntax elements and the principle of CABAC are firstly analyzed. Then guided by the spirit of parallel processing, a novel algorithm is constructed to estimate the bit-rate in RD mode decision. The proposed method significantly accelerates the encoding process while well maintaining the video quality, and is well suited to hardware implementations due to its feature of parallel processing1.

The HEVC (High Efficiency Video Coding) has risen as the state-of-the-art video coding standard, targeting the processing of high quality video. As one of its main components, the entropy encoding is based on the CABAC (Context-adaptive binary arithmetic coding) algorithm, which allows parallelization at higher video data representation (i.e. slices, tiles, and wavefront parallel processing) whereas posing serious challenges for low-level parallelization. Low-power dissipation is a sough-after goal for hardware video encoder designs, along with high performance. This work presents a hardware architecture for the sub-module BAE (Binary Arithmetic Encoder) of the CABAC, featuring low power techniques, such as clock gating and operand isolation. The techniques were inserted after a careful analysis, based on the statistical behavior of CABAC inputs for real video sequences. A 4-cores BAE core structure was implemented in order to provide high performance. As results, power reduction ranging 25--40% was achieved by applying the aforementioned techniques in specific parts of the architecture, while still accomplishing the requirements for UHD 8K real-time processing.

This paper investigates the effect of bit errors on H.264 decompression when Context-based Adaptive Binary Arithmetic Coding (CABAC) entropy coding is used. A set of simulations examines how often a single bit error in an H.264 slice causes a semantic error to be detected. This is called the Error Detection Probability (EDP). A high EDP implies a high certainty that, when no error is detected, there are no bit errors in the slice. A second set of simulations examines how long it takes for a semantic error to be detected when a bit error occurs. This measure is called the Error Detection Delay (EDD). The results of the simulations show the probability of the EDD as a function of bit distance. A third set of simulations examines the effect of undetected bit errors on decompression. The results show that undetected bit errors do not cause noticeable video quality degradation. The results of the three simulations may be used in an H.264 transmission scheme that uses semantic information as an indication of slice correctness.