Keynote Microprocessor Architectures for the Mobile Internet Era

In this paper the authors present a dual issue queued pipelined Java processor TRAJA 3.0. It can decode 162 instructions of the Java Virtual Machine (JVM)'s opcodes and it has a set of proprietary instructions. The pipeline has four instruction buffers and four decode queues to overcome the pipeline stalls on decoding the variable length instructions of the JVM. The processor also executes a restricted set of instruction folding and a restricted set of instruction reorder. In addition it has a caching scheme for the fast execution of the array instructions of the JVM.

Enhanced bifunctional electrocatalysis of Co5.47N nanocrystals in porous carbon nanofibers for high-efficiency zinc-air batteries

Extremely low loading of carbon quantum dots for high energy density in polyetherimide nanocomposites

Critical role of CuO doping on energy storage performance and electromechanical properties of Ba0.8Sr0.1Ca0.1Ti0.9Zr0.1O3 ceramics

The commercial sector in Europe consumes a lot of energy and has one of the highest rates of energy consumption in supermarkets. Thus, supermarkets are an important part for the purposes of meeting the targets for reducing greenhouse gases which Europe has set as 10% by 2020. This article discusses the potential of economic and energy consumption savings in addition to the reduction in greenhouse gases that a high energy efficiency air conditioning installation can have in supermarkets. An analysis of the air conditioning installation is carried out in a commercial infrastructure considered as a model. Exploring the way energy is used at different times of the year and comparing the results obtained from a traditional duct installation and a high energy efficiency installation. High energy efficiency installation uses inverter technology and energetically takes advantage of the residual heat from industrial cooling processes. When high energy efficiency system is used for supermarket air conditioning, the savings in electricity consumption vary between 56 and 62%, reducing CO2 emissions to less than half with a payback period in high energy efficiency installation of three-to-four years and this reduces the ecological footprint of the products sold in supermarkets.

Realization of spiking neural network (SNN) hardware with high energy efficiency and high integration may provide a promising solution to data processing challenges in future internet of things (IoT) and artificial intelligence (AI). Recently, design of multi-core reconfigurable SNN chip based on resistive random-access memory (RRAM) is drawing great attention, owing to the unique properties of RRAM, e.g., high integration density, low power consumption, and processing-in-memory (PIM). Therefore, RRAM-based SNN chip may have further improvements in integration and energy efficiency. The design of such a chip will face the following problems: significant delay in pulse transmission due to complex logic control and inter-core communication; high risk of digital, analog, and RRAM hybrid design; and non-ideal characteristics of analog circuit and RRAM. In order to effectively bridge the gap between device, circuit, algorithm, and architecture, this paper proposes a simulation model—FangTianSim, which covers analog neuron circuit, RRAM model and multi-core architecture and its accuracy is at the clock level. This model can be used to verify the functionalities, delay, and power consumption of SNN chip. This information cannot only be used to verify the rationality of the architecture but also guide the chip design. In order to map different network topologies on the chip, SNN representation format, interpreter, and instruction generator are designed. Finally, the function of FangTianSim is verified on liquid state machine (LSM), fully connected neural network (FCNN), and convolutional neural network (CNN).

Managed language runtimes such as the Java Virtual Machine (JVM) provide adequate performance for a wide range of applications, but at the same time, they lack much of the low-level control that performance-minded programmers appreciate in languages like <pre>C/C++</pre>. One important example is the intrinsics interface that exposes instructions of SIMD (Single Instruction Multiple Data) vector ISAs (Instruction Set Architectures). In this paper we present an automatic approach for including native intrinsics in the runtime of a managed language. Our implementation consists of two parts. First, for each vector ISA, we automatically generate the intrinsics API from the vendor-provided XML specification. Second, we employ a metaprogramming approach that enables programmers to generate and load native code at runtime. In this setting, programmers can use the entire high-level language as a kind of macro system to define new high-level vector APIs with zero overhead. As an example use case we show a variable precision API. We provide an end-to-end implementation of our approach in the HotSpot VM that supports all 5912 Intel SIMD intrinsics from <pre>MMX</pre> to <pre>AVX-512</pre>. Our benchmarks demonstrate that this combination of SIMD and metaprogramming enables developers to write high-performance, vectorized code on an unmodified JVM that outperforms the auto-vectorizing HotSpot just-in-time (JIT) compiler and provides tight integration between vectorized native code and the managed JVM ecosystem.

In-memory computing (IMC) has been proposed to overcome the von Neumann bottleneck in data-intensive applications. However, existing IMC solutions could not achieve both high parallelism and high flexibility, which limits their application in more general scenarios: As a highly parallel IMC design, the functionality of a MAC crossbar is limited to the matrix-vector multiplication; Another IMC method of logic-in-memory (LiM) is more flexible in supporting different logic functions, but has low parallelism. To improve the LiM parallelism, we are inspired by investigating how the single-instruction, multiple-data (SIMD) instruction set in conventional CPU could potentially help to expand the number of LiM operands in one cycle. The biggest challenge is the inefficiency in handling non-continuous data in parallel due to the SIMD limitation of (i) continuous address, (ii) limited cache bandwidth, and (iii) large full-resolution parallel computing overheads. This article presents GRAPHIC, the first reported in-memory SIMD architecture that solves the parallelism and irregular data access challenges in applying SIMD to LiM. GRAPHIC exploits content-addressable memory (CAM) and row-wise-accessible SRAM. By providing the in-situ, full-parallelism, and low-overhead operations of address search, cache read-compute-and-update, GRAPHIC accomplishes high-efficiency gather and aggregation with high parallelism, high energy efficiency, low latency, and low area overheads. Experiments in both continuous data access and irregular data pattern applications show an average speedup of 5x over iso-area AVX-like LiM, and 3-5x over the emerging CAM-based accelerators of CAPE and GaaS-X in advanced techniques.

The Force Control of a Novel Variable Rotational Speed Hydraulic Pump-Controlled System Using Adaptive Fuzzy Controller with Self-tuning Fuzzy Sliding-mode Compensation

The increased global energy demand and pollution of environment due to the consumption of fossil fuels require utilization of energy generated from renewable energy sources such as wind, tidal and solar power. As the contribution of these energy resources grows the energy storage systems with high energy densities, efficiencies and long cycle life become increasingly important. Energy storage systems are needed at times of high energy demand by storing energy when in excess. In this regard supercapacitors (SCs) are considered as the most promising energy storage devices due to their high power density, short characteristic time constant, excellent coulombic reversibility (98% or higher), high energy efficiency (92 – 94%), long cycle life (over 106 cycles) and wide operation temperature range [1-3]. Porous carbon materials are the most promising electrode materials for portable SCs due to the high surface area, good electrical conductivity, good chemical stability, low gravimetric density and low cost [4,5]. The electrical energy accumulated in SCs depends on the electrochemically active surface area and, thus, on the porosity and hierarchical porous structure of a carbon material. In addition, the presence of mesopores in porous carbon materials determines the power density of SCs having a strong effect on the rate of mass transfer and adsorption rate of charge carriers inside the hierarchical porous matrix. Therefore, the characteristics of micro- and mesoporous carbon materials (especially the ratio of micropore and mesopore surface areas and pore volumes) have to be optimized to improve further the specific energy and power density of EDLCs [4,5]. The objective of this study was to investigate the applicability limits of carbon material derived from granulated white sugar (GWS carbon) by hydrothermal carbonization (HTC) method combined with subsequent zinc chloride activation step of hydrochar, for SC electrodes. Synthesized GWS carbon material was used as an electrode material in SC cell filled with 1 M triethylmethylammonium tetrafluoroborate (TEMABF4) solution in acetonitrile (AN) or 1-ethyl-3-methylimidazolium tetrafluoroborate ionic liquid (EMImBF4) as the electrolytes. Cyclic voltammetry (CV), constant current charge/discharge (CC), electrochemical impedance spectroscopy (EIS) and constant power discharge (CP) methods were used to study the electrochemical performance of EDLC. The EIS, CV and CC measurement results show that the values of specific capacitance are somewhat higher for EMImBF4 (135 F g-1) electrolyte compared to the TEMABF4 in AN (110 F g-1). The CP test results show that at low constant power values the stored energy is higher for EDLC based on EMImBF4 ionic liquid (48 W h kg-1) compared with EDLC based on TEMABF4 in AN electrolyte (39 W h kg-1). However, the best capacitance retention, shortest relaxation time constant and substantially higher energy density delivered at higher constant power values were established for SC cell in 1 M TEMABF4 solution in AN due to the lower viscosity and higher electrical conductivity compared to the ionic liquid based electrolyte [5]. Acknowledgements This research was supported by the EU through the European Regional Development Fund (Centers of Excellence, 2014-2020.4.01.15-0011 and 3.2.0101–0030, TeRa project SLOKT12026T. Higher education specialization stipends in smart specialization growth areas 2014-2020.4.02.16-0026) and Institutional Research Grant IUT20–13. This work was partially supported by Estonian Research Council grants PUT1033 and PUT55.

Real-time performance is the primary requirement for edge computing systems. However, with the surge in data volume and the growing demand for computing power, a computing framework consisting solely of CPUs is no longer competent. As a result, CPU+ heterogeneous architecture using accelerators to improve edge computing systems' computing capacity has received great attention. The type of accelerators determines the performance of the edge computing system largely. The accelerators include Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). FPGAs with its reconfigurability and high energy efficiency are widely used in many edge computing scenarios. Nontheless, the performance depends also on the scheduling efficiency between software tasks on CPUs and hardware tasks on FPGAs. Unfortunately, the existing strategies have not fully exploited the differences between hardware and software tasks, thus resulting in low scheduling efficiency. This paper proposes a task scheduling framework on the Dynamic Partial Reconfiguration (DPR) platform. We take full account of the characteristics of task switching overhead and predictable execution time of hardware tasks in DPR, and reduce the number of task-switching times and active tasks in the system, thus improving the scheduling efficiency. We conduct a set of experiments on the Zynq platform to verify the proposed framework. Experimental results demonstrate that when the execution time of the accelerator exceeds the reconfiguration cost by an order of magnitude, the efficiencies of all the cases are more than 98%, and the efficiencies can reach 90%-98% in the same order of magnitude.

We describe the design issues in an implementation of the ESA/390 architecture based on binary translation to a very long instruction word (VLIW) processor. During binary translation, complex ESA/390 instructions are decomposed into instruction “primitives” which are then scheduled onto a wide-issue machine. The aim is to achieve high instruction level parallelism due to the increased scheduling and optimization opportunities which can be exploited by binary translation software, combined with the efficiency of long instruction word architectures. A further aim is to study the feasibility of a common execution platform for different instruction set architectures, such as ESA/390, RS?6000, AS/400 and the Java Virtual Machine, so that multiple systems can be built around a common execution platform.

Li–CO2 batteries are considered one of the promising power sources owing to ultrahigh energy density and carbon fixation. Nevertheless, the sluggish reaction kinetics of 4e− discharged process (Li2CO3) impede its potential application. One of the efficient strategies for developing cathode catalysts is to stabilize 2e− intermediate Li2C2O4 and improve reaction reversibility. However, long‐term catalysts of stabilized Li2C2O4 are barely achieved, whereas cycle stability is far from satisfactory level. Herein, non‐noble metal–based Mo3N2 is synthesized and employed as freestanding cathodes for Li–CO2 batteries. Owing to rich delocalized electrons of Mo2+ and reversible electron localization structure, freestanding Mo3N2 cathodes exhibit a low charge potential (3.28 V) with an ultralow potential gap (0.64 V), high energy efficiency of up to 80.46%, fast rate capability, and outstanding cycle stability (&gt;910 h). In situ experiments and theoretical calculation verify that Mo3N2 stabilizes 2e− Li2C2O4 intermediate by the interaction of Mo2+ as active sites where Mo2+ promotes the transfer of outer electrons to O, prevents its disproportionation to Li2CO3, and promotes reaction kinetics, contributing to high energy efficiency and outstanding cycle reversibility. In addition, the pouch‐cells deliver ultrahigh energy density of up to 6350.7 W h kg−1 based on the mass of cathode materials.

The rapid development of wearable electronics requires a revolution of power accessories regarding flexibility and energy density. The Li-CO2 battery was recently proposed as a novel and promising candidate for next-generation energy-storage systems. However, the current Li-CO2 batteries usually suffer from the difficulties of poor stability, low energy efficiency, and leakage of liquid electrolyte, and few flexible Li-CO2 batteries for wearable electronics have been reported so far. Herein, a quasi-solid-state flexible fiber-shaped Li-CO2 battery with low overpotential and high energy efficiency, by employing ultrafine Mo2 C nanoparticles anchored on a carbon nanotube (CNT) cloth freestanding hybrid film as the cathode, is demonstrated. Due to the synergistic effects of the CNT substrate and Mo2 C catalyst, it achieves a low charge potential below 3.4 V, a high energy efficiency of ≈80%, and can be reversibly discharged and charged for 40 cycles. Experimental results and theoretical simulation show that the intermediate discharge product Li2 C2 O4 stabilized by Mo2 C via coordinative electrons transfer should be responsible for the reduction of overpotential. The as-fabricated quasi-solid-state flexible fiber-shaped Li-CO2 battery can also keep working normally even under various deformation conditions, giving it great potential of becoming an advanced energy accessory for wearable electronics.

Experimental study on a coiled tube solar receiver under variable solar radiation condition