Kite attack: reshaping the cube attack for a flexible GPU-based maxterm search

With black-box access to the cipher being its unique requirement, Dinur and Shamir’s cube attack is a flexible cryptanalysis technique which can be applied to virtually any cipher. However, gaining a precise understanding of the characteristics that make a cipher vulnerable to the attack is still an open problem, and no implementation of the cube attack so far succeeded in breaking a real-world strong cipher. In this paper, we present a complete implementation of the cube attack on a GPU/CPU cluster able to improve state-of-the-art results against the Trivium cipher. In particular, our attack allows full key recovery up to 781 initialization rounds without brute-force, and yields the first ever maxterm after 800 initialization rounds. The proposed attack leverages a careful tuning of the available resources, based on an accurate analysis of the offline phase, that has been tailored to the characteristics of GPU computing. We discuss all design choices, detailing their respective advantages and drawbacks. Other than providing remarkable results, this paper shows how the cube attack can significantly benefit from accelerators like GPUs, paving the way for future work in the area.

Cube attacks are an important type of key recovery attacks against stream ciphers. In particular, they are shown to be powerful against Trivium-like ciphers. Traditional cube attacks are experimental attacks which could only exploit cubes of size less than 40. At CRYPTO 2017, division property based cube attacks were proposed by Todo et al., and an advantage of introducing the division property to cube attacks is that large cube sizes which are beyond the experimental range could be explored, and so powerful theoretical attacks were mounted on many lightweight stream ciphers.In this paper, we revisit the division property based cube attacks. There is an important assumption, called Weak Assumption, proposed in division property based cube attacks to support the effectiveness of key recovery. Todo et al. in CRYPTO 2017 said that the Weak Assumption was expected to hold for theoretically recovered superpolies of Trivium according to some experimental results on small cubes. In this paper, it is shown that the Weak Assumption often fails in cube attacks against Trivium, and moreover a new method to recover the exact superpoly of a given cube is developed based on the bit-based division property. With our method, for the cube I proposed by Todo et al. at CRYPTO 2017 to attack the 832-round Trivium, we recover its superpoly pI(x, v) = v68v78 · (x58⊕v70) · (x59x60⊕x34⊕x61). Furthermore, we prove that some best key recovery results given at CRYPTO 2018 on Trivium are actually distinguishing attacks. Hopefully this paper gives some new insights on accurately recovering the superpolies with the bit-based division property and also attract some attention on the validity of division property based cube attacks against stream ciphers.

The security analysis of Keccak, the winner of SHA-3, has attracted considerable interest. Recently, some attention has been paid to the analysis of keyed modes of Keccak sponge function. As a notable example, the most efficient key recovery attacks on Keccak-MAC and Keyak were reported at EUROCRYPT’15 where cube attacks and cube-attack-like cryptanalysis have been applied. In this paper, we develop a new type of cube distinguisher, the conditional cube tester, for Keccak sponge function. By imposing some bit conditions for certain cube variables, we are able to construct cube testers with smaller dimensions. Our conditional cube testers are used to analyse Keccak in keyed modes. For reduced-round Keccak-MAC and Keyak, our attacks greatly improve the best known attacks in key recovery in terms of the number of rounds or the complexity. Moreover, our new model can also be applied to keyless setting to distinguish Keccak sponge function from random permutation. We provide a searching algorithm to produce the most efficient conditional cube tester by modeling it as an MILP (mixed integer linear programming) problem. As a result, we improve the previous distinguishing attacks on Keccak sponge function significantly. Most of our attacks have been implemented and verified by desktop computers. Finally we remark that our attacks on the reduced-round Keccak will not threat the security margin of Keccak sponge function.

Currently the set of scientific applications suitable for running on GPUs has increased due to the computational power of GPUs and the availability of programming languages that make more approachable writing scientific applications for GPUs. However, as the size of the problems increases, the global memory of GPUs becomes a limitation for running applications.Multi-GPU systems can potentially make memory limited problems tractable by dividing the data and computation among several GPUs. Parallel execution is seriously limited by the (i) application data dependencies, and (ii) data transfers among GPUs.In this paper we analyze the potential for parallelization of unstructured grid applications based on the data dependencies of the algorithm and the amount of data communication required. Due to data dependencies and the required communication, data and task parallelization techniques present different communication overheads and computing devices utilization. Based on this analysis we propose a scheme that takes advantage of data and task parallelism and reduces the communication overhead through computation-communication overlap. Our OpenCL implementation reduces the communication overhead by 38%, and, for comparison purposes, a two GPU implementation provides almost a five-fold increase in performance as compared to a CPU implementation.

This paper describes electromagnetical field simulation using the 3D-FDTD method for antenna designing on a CUDAcompatible GPU. We use the Split Perfectly Matched Layer as an absorbing boundary condition. As is well known, the 3D-FDTD method is a kind of stencil computation and is considered better at GPU implementation. In order to find the best blocking size for the target GPU architecture, we empirically explore a design space of blocking size. We also propose a kernel fusing method as one of the efficient optimization methods, which improves the total performance about 10% at the cost of a small increase in memory usage. As a result of evaluation, our implementation of the 3D-FDTD method on a GeForce GTX295 platform achieves about 130 times performance improvement compared to a simple CPU implementation, which is expected to be faster than an ideally parallelized CPU implementation using multicore and SIMD instructions.

The Partitioned Global Address Space (PGAS) approach is a promising programming model in high performance parallel computing that combines the advantages of distributed memory systems and shared memory systems. The PGAS model has been used on a variety of hardware platforms in the form of PGAS programming languages like Unified Parallel C (UPC), Chapel and Fortress. However, in spite of the increasing adoption in distributed and shared memory systems, the extension of the PGAS model to accelerator platforms is still not well supported. To exploit the immense computational power of multi-GPU systems, this work is concerned with the design and implementation of a Partitioned Global Address Space model for multi-GPU systems. Several issues related to the combination of logically separate GPU memories on multiple graphic cards are addressed. Furthermore, the execution model of modern GPU architectures is studied and a task creation mechanism with load balancing is proposed. Our work is implemented in the context of the DASH project, a C++ template library that realizes PGAS semantics through operator overloading. Experimental results suggest promising performance of the design and its implementation.

Basic Linear Algebra Subprograms (BLAS) are a set of low level linear algebra kernels widely adopted by applications involved with the deep learning and scientific computing. The massive and economic computing power brought forth by the emerging GPU architectures drives interest in implementation of compute-intensive level 3 BLAS on multi-GPU systems. In this paper, we investigate existing multi-GPU level 3 BLAS and present that 1) issues, such as the improper load balancing, inefficient communication, insufficient GPU stream level concurrency and data caching, impede current implementations from fully harnessing heterogeneous computing resources; 2) and the inter-GPU Peer-to-Peer(P2P) communication remains unexplored. We then present BLASX: a highly optimized multi-GPU level-3 BLAS. We adopt the concepts of algorithms-by-tiles treating a matrix tile as the basic data unit and operations on tiles as the basic task. Tasks are guided with a dynamic asynchronous runtime, which is cache and locality aware. The communication cost under BLASX becomes trivial as it perfectly overlaps communication and computation across multiple streams during asynchronous task progression. It also takes the current tile cache scheme one step further by proposing an innovative 2-level hierarchical tile cache, taking advantage of inter-GPU P2P communication. As a result, linear speedup is observable with BLASX under multi-GPU configurations; and the extensive benchmarks demonstrate that BLASX consistently outperforms the related leading industrial and academic implementations such as cuBLAS-XT, SuperMatrix, MAGMA.

We present a GPU implementation to compute both mutual information and its derivatives. Mutual information computation is a highly demanding process due to the enormous number of exponential computations. It is therefore the bottleneck in many image registration applications. However, we show that these computations are fully parallizable and can be efficiently ported onto the GPU architecture. Compared with the same CPU implementation running on a workstation level CPU, we reached a factor of 170 in computing mutual information, and a factor of 400 in computing its derivatives.

In this article, we present a parallel prioritized Jacobian-based inverse kinematics algorithm for multithreaded architectures. We solve damped least squares inverse kinematics using a parallel line search by identifying and sampling critical input parameters. Parallel competing execution paths are spawned for each parameter in order to select the optimum that minimizes the error criteria. Our algorithm is highly scalable and can handle complex articulated bodies at interactive frame rates. We show results on complex skeletons consisting of more than 600 degrees of freedom while being controlled using multiple end effectors. We implement the algorithm both on multicore and GPU architectures and demonstrate how the GPU can further exploit fine-grain parallelism not directly available on a multicore processor. Our implementations are 10 to 150 times faster compared to a state-of-the-art serial implementation while providing higher accuracy. We also demonstrate the scalability of the algorithm over multiple scenarios and explore the GPU implementation in detail.

Hyperspectral imaging can be used for object detection and for discriminating between different objects based on their spectral characteristics. One of the main problems of hyperspectral data analysis is the presence of mixed pixels, due to the low spatial resolution of such images. This means that several spectrally pure signatures (endmembers) are combined into the same mixed pixel. Linear spectral unmixing follows an unsupervised approach which aims at inferring pure spectral signatures and their material fractions at each pixel of the scene. The huge data volumes acquired by such sensors put stringent requirements on processing and unmixing methods. This paper proposes an efficient implementation of a unsupervised linear unmixing method on GPUs using CUDA. The method finds the smallest simplex by solving a sequence of nonsmooth convex subproblems using variable splitting to obtain a constraint formulation, and then applying an augmented Lagrangian technique. The parallel implementation of SISAL presented in this work exploits the GPU architecture at low level, using shared memory and coalesced accesses to memory. The results herein presented indicate that the GPU implementation can significantly accelerate the method's execution over big datasets while maintaining the methods accuracy.

Vertex coloring is an assignment of colors to vertex of an undirected graph such that no two vertices sharing the same edge have the same color. The vertex coloring problem is to find the minimum number of colors necessary to color a graph given, which is an NP-hard problem in combinatorial optimization. Ant Colony Optimization (ACO) is a well-known meta-heuristic in which a colony of artificial ants cooperates in exploring good solutions to a combinatorial optimization problem. Several methods applying ACO to the vertex coloring problem have been proposed. The main contribution of this paper is to propose a GPU implementation to accelerate the computation of the ACO algorithm for the vertex coloring problem. In our implementation, we have considered programming issues of the GPU architecture, such as coalescing access of the global memory, bank conflict of the shared memory, etc. The experimental results show that on NVIDIA GeForce GTX 1080, our implementation for 1000 vertices runs in 2.740s, while the CPU implementation on Intel Core i7-4790 runs in 100.866s. Thus, our GPU implementation attains a speed-up factor of 36.81.

The Floyd-Warshall algorithm is a well-known algorithm to compute the distance of all pairs of nodes of a graph. The Blocked Floyd-Warshall algorithm, a variant of the Floyd-Warshall has been proposed to accelerate the Floyd-Warshall algorithm by means of a GPU architecture. The previously published GPU implementations for the Blocked Floyd-Warshall algorithm perform many separated kernel calls for costly barrier synchronization. The main contribution of this paper is to present a more sophisticated implementation of the Blocked Floyd-Warshall algorithm, which performs no barrier synchronization and invokes only one kernel call. Experimental results using NVIDIA Tesla V100 show that our implementation is 1.02-1.09 times faster than the previously published one. Our implementation with SIMD functions also runs 1.22-2.02 times faster than it. Furthermore, we propose efficient GPU implementations to execute the Blocked Floyd-Warshall algorithm for many graphs at the same time. From the experimental results, our implementation is 1.02-1.46 times faster than an extended implementation of previous one.

Model-Based Iterative Reconstruction (MBIR) algorithms iteratively use expensive computational operators of forward and backward projections. The irregular memory access pattern of these operators makes them a memory-bound application. Their computation time must be reduced to meet clinical routine constraints. This paper proposes a hardware accelerator architecture based on Field Programmable Gate Arrays (FPGAs) through high-level language, as an alternative to GPU architecture. This acceleration is based on an offline memory access analysis to address the main bottleneck of the algorithm and maximize the data reuse rate. The offline analysis allows for the tuning of the architecture parameters so that they converge to an optimal solution. Then, the Berkeley Roofline model guides our optimization steps by iteratively analyzing the design performance. Our design flow significantly improved the algorithm's computational intensity and overcame the memory bottleneck. Thus, our architecture takes advantage of the FPGA local memory to achieve significant memory bandwidth and efficiently harness the pipeline without stalling the computation. Furthermore, we present the scaling-up strategy from mid-range FPGA to high-end FPGA and any concerns of portability. We used two Intel FPGA devices to implement the algorithm, and then we compared the results with our GPU implementation in terms of speedup and energy efficiency. Our experimental results show that our design has achieved better computational throughput than the works on FPGA architectures reported in the literature.

The Inferior Olive (IO) in the brain, in conjunction with the cerebellum, is responsible for crucial sensorimotor-integration functions in humans. In this paper, we simulate a computationally challenging IO neuron model consisting of three compartments per neuron in a network arrangement on GPU platforms. Several GPU platforms of the two latest NVIDIA GPU architectures (Fermi, Kepler) have been used to simulate large-scale IO-neuron networks. These networks have been ported on 4 diverse GPU platforms and implementation has been optimized, scoring 3x speedups compared to its unoptimized version. The effect of GPU L1-cache and thread block size as well as the impact of numerical precision of the application on performance have been evaluated and best configurations have been chosen. In effect, a maximum speedup of 160x has been achieved with respect to a reference CPU platform.

PurposeTotal quality management practices have been embraced by many quality-oriented firms around the world in order to improve performance in terms of quality, productivity, customer satisfaction and profitability. The purpose of this paper is to investigate the direct and indirect effects of TQM practices on various performance indicators specifically in the Indian manufacturing context. This paper focuses on developing an integrated model encompassing significant structural relations showing the linkage between TQM practices and multiple performance indicators – quality performance, customer satisfaction level, operating performance, employee performance, innovation performance, society results and financial performance. Apart from analyzing the direct relationship between constructs, the main purpose of this work is also to identify all the possible mediation effects of performance indicators on others using structural equation modeling (SEM).Design/methodology/approachAn in-depth literature review was conducted to identify the key practices for the successful implementation of TQM in an organization as well as to explore TQM-performance effects. As a result, four TQM practices and seven performance indicators were identified. The data were collected from 260 Indian manufacturing organizations. After confirming the reliability and validity using exploratory and confirmatory factor analysis, the proposed hypotheses were tested using SEM.FindingsThrough testing the proposed hypothesized structural model, the direct and indirect effects of TQM practices have been examined. Moreover, this work developed an integrated model showing the interrelationships between TQM practices and performance indicators identified. The findings gave an insight that the effective implementation of TQM practices assists in reaping benefits in the every facet of an organization. By implementing these practices effectively, managers can expect to realize improvement in all these performance areas.Research limitations/implicationsThis study is subject to certain limitations. Even if all variables were found to be reliable, valid and satisfactory non-response bias test results, the remote possibility of bias in the data might not be fully ruled out. There is a probability of occurrence of common method variance and common method bias, since the data for both dependent and independent variables were collected from the same respondents in the organization. Additionally data on performance indicators were based on the respondent’s assessment and awareness only. The mediating relationship between individual TQM practice and performance indicators can be investigated in future studies. Since society results are a necessity in future, the direct and indirect practices focusing toward this can be explored. In addition, there is a research scope to identify the moderating effect of contextual factors such as degree of TQM implementation, scope of operation and type of organization.Practical implicationsThe findings of the research offer some potentially valuable insights into the relevance of TQM practices and its strong linkage on various performance indicators, through which the overall organization performance can be enhanced. By implementing these practices effectively, managers can expect to realize improvement in all these performance areas. Hence, the managers can adopt this approach to assess their organization’s level in the quality path and as a guideline in implementing TQM practices. They can also measure the impacts of TQM practices on multiple performance measures in order to evaluate their TQM initiatives. Especially the deployment of quality culture is a requisite to excel in the every facet of performance. The positive relationship between TQM practices and various performance indicators can motivate the managers to allocate resources in time, effort and capital for TQM implementation in pursuing quality, leading to customer retention and competitiveness. The findings of the study strongly suggest the need for the holistic implementation of TQM practices for the survival of the organization.Originality/valueWhile there is a considerable volume of researches carried out to investigate the linkage between TQM and organization’s performance across the globe, still little is evidenced regarding the mediating effect of performance indicators on others, especially in the Indian manufacturing context. The present paper attempts to extend and add knowledge to this line of research and to bridge the gap and provide sufficient empirical evidence specifically in the Indian scenario. Thereby helps the organization to follow a guideline to improve the overall performance.