Knowledge representation and reasoning in a software synthesis architecture

According to some casual observers, computer-aided design (CAD) tools are very similar. These tools are used to design new artifacts in a digital environment; hence, they share typical software components, such as a computing engine and human–machine interface. However, CAD software is dedicated to specific professionals – such as engineers, three-dimensional (3D) artists, and industrial designers (IDs) – who claim that, despite their apparent similarities, CAD tools are so different that they are not substitutable. Moreover, CAD tools do not fully meet the needs of IDs. This paper aims at better characterizing CAD tools by taking into account their underlying design logic, which involves relying on recent advances in design theory. We show that engineering CAD tools are actually modeling tools that design a generic variety of products; 3D artist CAD tools not only design but immediately produce single digital artifacts; and ID CAD tools are neither a mix nor an hybridization of engineering CAD and 3D artist CAD tools but have their own logic, namely to create new conceptual models for a large variety of products, that is, the creation of a unique original style that leads to a generic singularity. Such tools are useful for many creative designers beyond IDs.

The frame transfer Area Array Sensor with vertical antiblooming structure requires that all performance characteristics such as large charge capacity, high charge transfer efficiency, low read noise and low antiblooming voltage be optimized in a singlemanufacturable CCD (charge-coupled device). There is a common tendency to optimize one performance characteristic at the expense of others. With the goal of optimizing above all performance characteristics, a frame transfer area array sensors with vertical antiblooming structure is optimization designed by the CAD (computer aided design) tools and fabricated, which equal to twenty-six micron square pixel size with 516 (H) x1028 (V) active pixels(the channel stop is 4μm and the photosensitive area is 22x22 μmxμm). At first, it is simply introduced the modeling of the frame transfer area array sensors with vertical antiblooming structure from the top to down and simulated by the CAD tools combined with the process and device models. The essential design and calculation of the CCD with antiblooming function are discussed in detail. And the process, layout and device parameters to design this frame transfer area array sensors (including the impurity concentration and layer thickness of the P-well and the buriedchannel, and the design output amplifier) are optimized according to the above simulation. At the last, the device is fabricated and the performance characteristics ( e.g. charge capacity, charge transfer efficiency, read noise and antiblooming voltage) are test to compare the simulation. To demonstrate the process used to optimize this frame transfer area array sensors with vertical antiblooming structure, this paper contains test data for this kind of CCD device which is optimization designed and fabricated by the CAD (computer aided design) tools. The test datas shows the way using the CAD tools optimization design a frame transfer area array sensors with vertical antiblooming structure correct.

Rough set based lattice structure for knowledge representation in medical expert systems: Low back pain management case study

Following the vision of Industry 4.0, manufacturers started to break down products into subsystems, each of which is developed and supplied by different suppliers to tackle the increasing complexity of product development (e.g., in vehicle, machine or plant construction). This process needs to be supported by intuitive Computer-Aided Design (CAD) tools and virtual modeling and simulation environments to effectively meet the challenges of increasingly complex product development. Therefore, in this paper, we present some outcoming of a research project called DisMoSim ( Dis tributed Mo deling and Sim ulation), which proposes an intuitive virtual environment for modeling and simulation that embeds a Multi User Inverse Kinematic Solver (MUKS). The MUKS allows (i) individual subsystems to be tested intuitively, i.e., Rapid Testing (RT), and (ii) people not yet familiar with a subsystem to understand it easily and quickly through simple kinematic actions, i.e., Rapid Understanding (RU), without unnaturally interrupting the modeling process. Finally, (iii) the MUKS enables subsystems to be easily assembled into complete systems, i.e., Rapid Assembling (RA), by means of a so-called snapping-point mechanism which supports the complex process of aligning and assembling different subsystems. To evaluate these capabilities, we present the results of a user study conducted with 20 participants. Special attention has been given to the embedded MUKS in contrast to existing approaches known from common CAD and simulation software. Thus, we demonstrate the practicability, usability, and versatility of our approach. • Finding modeling and simulation errors in CAD models is cumbersome with current tools. • CAD tools need intuitive means for testing during modeling. • Inverse kinematic solvers allow for rapid prototyping and testing in CAD systems. • New user interface and interaction paradigms ease interaction with CAD tools.

Additive manufacturing has opened the door to the creation of lightweight lattice structures. However, present Computer-Aided Design (CAD) and Computer-Aided Engineering (CAE) software are unsuitable for these types of structures. The objective of this research is to examine the performances of current CAD and CAE software to design lattice structures and to demonstrate their limitations and propose requirements for future developments. A performance evaluation of a case study for lattice structure designs was conducted. The criteria used for the evaluation were CAD human-machine-interface, RAM consumption, data exchange between CAD, CAE and CAM tools and finite element analysis (FEA) duration and file sizes. The CAD tool was incapable of executing a repetition function for octet-truss lattice structures of 150 x 150 x 150 mm dimensions or larger and the software stopped working. For 70 × 70 × 70 mm octet-truss lattice structure, the FEA computation file size reached 36.6 GB. The CAD file size of a 200 x 200 x 200 mm octet-truss lattice structure reached nearly 290 MB. In conclusion, this study exposes the performance inadequacy of current CAD and CAE tools and CAD file formats to design lattice structures for additive manufacturing parts.

This paper presents the efforts to introduce integrated circuit (IC) design to Electronics engineering undergraduate students, using the LASI program. The professional Computer-aided Design (CAD) systems for IC design are expensive in terms of hardware, CAD tools and CAD licenses. The next problem connected to their use for educational purposes is the need of training on both the CAD software and the UNIX system. The Windows LASI system is a freeware CAD environment for a full-custom Very Large Scale Integration (VLSI) microelectronic circuits design, intended for educational purposes. The LASI tool is employed for teaching IC design in Electronics engineering undergraduate program at the Department of Electronics, Ruse University, Bulgaria. The paper provides description of the Microelectronics courses, LASI system, technology, and an example design.

One way to enhance students’ ability to visualize 3-D objects is to make their experience of the objects, while learning, as realistic as possible. However, in general, it is very difficult to clearly describe to students a 3-D object and the spatial relationship between the object components, without using a physical mockup. Physical mockups take a lot of time to construct, especially for more complex objects. As a result, graphics educators have started to use 3-D computer-aided design (CAD) tools to help students understand the spatial relationships between objects. However, CAD tools only allow students to examine 3-D models from outside flat computer monitors. In other words, the models and the viewers are in different realms. Using traditional CAD tools, students cannot view models with natural stereoscopic vision. Virtual reality (VR) is a computer technology of simulating or replicating a physical environment to give users a sense of being there, taking control, and physically interacting with the environment (Ausburn & Ausburn, 2004). VR technology breaks down barriers between humans and computers by immersing viewers in a computer-generated stereoscopic environment. With advances in hardware and software, most PC computers now have the capability to support VR use. Thus, VR has now become an affordable visualization tool that can be used in classrooms. As Ausburn and Ausburn (2004) indicated, there is a significant opportunity to expand and explore the use of VR in classrooms. Research suggests that VR is an effective tool that enhances learning in areas such as engineering (Sulbaran & Baker, 2000). In addition, VR engages the intellectual, social, and emotional processes of learners. The impact of VR is due to its ability to encourage interaction and ability to motivate learners (Winn et al., 1997). Salzman (1999) found that VR applications in education depends on VR features, class contents, students’ characteristics, and students’ prior experiences. The emphasis of engineering graphics education has been placed on design, problemsolving, presentation, and communication skills. Three dimensional spatial visualization ability is the core requirement for successfully developing those skills. The use of VR may also represent an effective strategy that supports the development of spatial skills. It is important to combine exposure to VR models with activities such as sketching or drawing as a means for developing a capacity for visual imagery and creativity (Deno, 1995; Devon et al., 1994; Sorby, 1999). Sorby (1999) explained that in most cases, graphics curricula begin with multi-view sketching/drawing and then move to pictorial sketching. However, this

Besides foundry facilities, Computer-Aided Design (CAD)tools are also required to move microsystems from researchprototypes to an industrial market. Currently available CADtools need extensions before they can be used for theautomated design of micromachined devices.This paper presents a low cost access to microsystemtechnology (MST), applied by the CMP service, and based onthe use of existing microelectronics production lines, withadditional post-processing for microsystem specific 2D and3D structures, and a global CAD approach for the design andsimulation of microsystems applied to currently availablecommercial CAD tools, e.g. Mentor Framework, in order toensure a continuous flow from the design to themanufacturing.

A Computer Aided Design (CAD) tool consisting of two new interconnect network routing algorithms is developed. It was developed to assist in manufacturing test development for any Programmable Logic Device (PLD) such as Complex Programmable Logic Devices (CPLDs) and/or Field Programmable Gate Array (FPGA) devices which utilize any interconnect network structure whose definition/connectivity and control can be described in a presented manner. The CAD tool utilizing the new routing algorithms supports manual and semiautomatic explicit, non-explicit, and net routing and was extensively tested on the interconnect networks of the Cypress Delta39K/sup TM/ series CPLD for the purpose of manufacturing testing of the programmable interconnect networks within the device as well as all programmable logic functions of the device. The two routing algorithms were developed and experimentally proved to work correctly with the best one chosen based on both theoretical and experimental complexity analysis and the particular routing scenario to be solved. The resultant routing CAD tool will produce the configuration bits necessary to program or configure PLD devices for the extensive tests that must be applied to ensure that the manufactured PLDs are defect-free. The router CAD tool can also be extensively used in the verification of the design process of PLDs as verified via experimental testing.

During the engineering product development cycle, while going through the concept ideation stage, it is very important to accelerate the thinking process and to represent concept ideas in front of colleagues to brainstorm and refine for faster product design and its development. Availability and use of different computer-aided design (CAD) tools in the market made this concept generation process longer and time-consuming due to its limitation on detailing and editing. As an alternative, freehand sketching is very quick and easily editable which focuses on quantity rather than quality which allows healthy discussion and quick adjustment towards a valid and relevant design proposal. To explore learner's (students') experiences of concept ideation while studying product design and development, different freehand sketching tools were introduced like the use of some software instead of just traditional pen and paper kind of freehand sketching during the start of the trimester to quickly represent their ideas amongst their peers. During the later part of detail design, they used CAD tools. In this paper, a few examples are provided to show students' freehand sketching skills during concept ideation and the use of CAD tools for detailed design drawing. The effectiveness of this approach is measured through a survey conducted for students at the end of the trimester and it has been evaluated based on the survey results. They were asked to give responses based on their experience during the trimester. The results suggest that it is very important to emphasize the use of freehand sketching during concept ideation and the utility of CAD tools at the detail design stage of the product design development to achieve the learning outcomes of the module of Design and Manufacture 1 at the University of Glasgow, Singapore (UGS).

Computer-aided design (CAD) tools throughout a design automation (DA) system, from low level physical design to high level resource allocation and scheduling tools, require information about the fabrication technology in order to make design decisions. Technology dependent information is maintained in technology files. As fabrication technologies evolve, these files must be updated to reflect the capabilities of the current fabrication process technology. Currently, the task of updating technology files is performed manually and often prone to error and inconsistencies. A system for the automatic updating of technology dependent information in a design automation system is presented. The technology information required by the CAD tools throughout a design automation system are consistent since they are all derived from a common source. >

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be Normally powered off, Instantly powered on. Second, by combining functionality of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS circuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis,we present high-performance and low-power RRAM-based FPGAs fromtransistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and electrical simulations. The proposed 4T(ransitor)1R(RAM) programming structure demonstrates significant improvements in programming current, when compared to most popular 2T1R programming structure. 4T1R-based routingmultiplexer designs are proposed by considering various physical design parasitics, such as intrinsic capacitance of RRAMs and wells doping organization. The proposed 4T1R-based multiplexers outperformbest CMOS implementations significantly in area, delay and power at both nominal and near-Vt regime. From a CAD perspective, we develop a generic FPGA architecture exploration tool, FPGASPICE, modeling a full FPGA fabric with SPICE and Verilog netlists. FPGA-SPICE provides different levels of testbenches and techniques to split large SPICE netlists, in order to obtain better trade-off between simulation time and accuracy. FPGA-SPICE can capture area and power characteristics of SRAM-based and RRAM-based FPGAs more accurately than the currently best analyticalmodels. From an architecture perspective, we propose architecture-level optimizations for RRAMbased FPGAs and quantify their minimumrequirements for RRAM devices. Compared to the best SRAM-based FPGAs, an optimized RRAM-based FPGA architecture brings significant reduction in area, delay and power respectively. In particular, RRAM-based FPGAs operating in the near-Vt regime demonstrate a 5x power improvement without delay overhead as compared to optimized SRAM-based FPGA operating at nominal working voltage.

As the modern integrated circuit continues to grow in complexity, the design of very large-scale integrated (VLSI) circuits involves massive teams employing state-of-the-art computer-aided design (CAD) tools. An old yet significant CAD problem for VLSI circuits is physical design automation. In physical design automation, we need to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface. The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for combinatorial circuits, there are several models for the clustering problem. In particular, we consider the problem of clustering without replication in combinatorial circuits with a view towards minimizing delay (CN). The corresponding problem with replication has been well-studied and solvable in polynomial time. However, replication can become expensive when it is unbounded. Consequently, CN is a problem worth investigating. We establish the computational complexities of several variants of CN. Additionally, we obtain approximability and inapproximability results for some NP-hard variants of CN. We also present approximation and exact exponential algorithms for some variants of CN. We prove that for some cases there exists an approximation factor of strictly less than two and that our exact exponential algorithms beat brute force. Furthermore, we provide the first parameterized approximation algorithm in which the approximation ratio is also a parameter.

As the very large scale integration (VLSI) technology approaches its fundamental scaling limit at about 0.2 /spl mu/m, it is reasonable to consider three-dimensional (3-D) integration to enhance packing density and speed performance. With additional functional units packed into one chip in a 3-D space, computer-aided design (CAD) tools are demanded to ease the complicated design work. This paper presents a 100% completion achievable routing methodology. The routing methodology is based on the two-dimensional (2D) channel routing methodology; thus, it is called a 3-D channel routing methodology. With the routing methodology, a 3-D routing problem is decomposed into two 2D routing subproblems: intra-layer routing that interconnects terminals on the same layer, which can be done by using a 2-D channel router, and inter-layer routing that interconnects terminals on different layers. The inter-layer routing problem is transformed into a 2-D channel routing problem and the transformation is made in some 3-D channels. Detailed discussions are given for the 3-D to 2-D transformation. Optimization of the transformation is shown to be NP-complete. Thus, simulated annealing is used to optimize the transformation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Emulation based on FPGA technology, for functional verification, is becoming a widespread practice for digital integrated circuit designers. One drawback to this debugging and testing technique is the lengthy time spent in the back-end computer-aided design (CAD) tools for each design iteration. Even for small and localized debugging changes large portions of the design are typically re-placed-and-routed. We have developed a more fine-grained approach that allows the CAD tools to re-place-and-route only the portions of the design affected by the debugging changes. This goal is achieved by partitioning the design at the physical level into independent components. Design changes are localized to the affected components, allowing more limited re-placement-and-routing. The result is a shorter time between emulation and debugging iterations, and thus a shorter time-to-market for the design. Experiments on two large designs and six smaller MCNC benchmarks quantify the reduced back-end CAD tool time.