Leakage minimization in full adder by using sub-threshold technique

In CMOS technology, performance degradation of power is one of the foremost questions at daily vitality. In this circuit, power dissipation is increasing exponentially constantly with technology scaling down. The analog to digital converters (ADCs) are the vital branch of signal processing and communication system. In digital region power consumption and low voltage develop into wide component is difficult for conniving high speed devices and converters. In this paper we have presented a complete investigation of 3 bits flash ADC circuit by using low leakage stacked power gating technique and diode based stacked power gating technique. These techniques are reduces the leakage current and average power in standby mode effectively. In this circuit, with the stacked power gating technique, leakage current and average power is reduced is by up to 77% and 99% respectively. Diode based stacked power gating technique can be identified as the most effective technique. With this technique, leakage current is 1.241 nA at 0.7 V and average power is 3.49 nW at 0.7 V. To evaluate of power gating techniques, the simulation has been performed using cadence virtuoso tool at assorted power supply by 45nm technology.

Motion estimation is the power-hungry block in the video compression system. The sum of absolute difference (SAD) is the most repeated operation in block matching algorithms of the motion estimation subsystem. This paper identifies low-power full adder that is used in the proposed SAD architecture. The proposed SAD method consumes low power as compared to the existing SAD architectures. The designs are implemented using ASIC flow (synthesis) using the Cadence tools and the simulations are done using the Modelsim simulation tools. The synthesis is done using TSMC 180 nm and 45 nm technology libraries; the synthesis is mainly focused on the power consumed, area acquired and latency. This paper implements 4 × 4 (16 input samples) SAD algorithm, and the proposed architecture shows 26.3 % improvement in leakage power, 67.58 % improvement in dynamic power, and 65.6 % improvement in the total power with the 180 nm technology and 13.9 % improvement in the leakage power, 62 % improvement in the dynamic power, and overall 60 % improvement of total power with the 45 nm technology, as compared to the existing architecture.

One of the benefits of coarse grained dynamically reconfigurable processor array(DRPA) is its low dynamic power consumption by operating a number of processing elements(PE) in parallel with low clock frequency. However, in the future advanced processes, leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to reduce the leakage power, a fine grained Power Gating(PG) is applied to a DRPA, MuCCRA-2.32b, and leakage power and area overhead are measured. We evaluated the effect of two control modes; Pair and Unit Individual based on layout design and real applications. It appears that by applying PG for ALUs and SMUs in PEs individually, 48% of leakage power can be reduced with 9.0% of area overhead.

As per the International Technology Roadmap for Semiconductors (ITRS) the leakage power is growing exponentially and is the major part of total power consumption in the integrated device. With the growing impact of subthreshold and gate leakage, static leakage contributes more and more towards the power dissipation in deep submicron nano CMOS technology. To overcome this problem several techniques has been proposed. In this paper we analyses the subthreshold leakage minimization techniques in circuit level. We propose a circuit technique named “Feedback Sleeper-Stack (FS-S)” for efficient leakage reduction in digital circuits. The proposed technique is compared with available leakage reduction techniques for subthreshold power, total power, delay and PDP (Power Delay Product). Of the available techniques, three power gating techniques are considered for comparison namely, Sleeper, Forced Stacking (FS) and Sleepy Stack (SS). Nominal supply voltage of 0.9V is selected and 32nm BSIM4 Predictive Technology Models (PTM) is employed in the analysis. ELDO Mentor Graphics tool is used for net list simulation.

Modular arithmetic computations are used widely in various data security and reliability techniques. Information security systems certainly benefit from the design of energy-efficient modular exponentiation architectures. The use of low-power logic adders to realize modular exponentiation operations is very essential in prospective cryptography contexts. In this paper, various full adder circuit designs are presented which are used in developing an energy efficient modular exponentiation architecture. Here, the full adder is designed using Register Transfer Level (RTL), Standard Logic Cell (SLC), Reversible Logic Gate (RLG), and Artificial Neural Network (ANN) logic methods. All full adder designs are imposed on modular exponentiation circuit to analyze performance metrics in terms of dynamic power dissipation, Figure of Merit, and Energy Delay Product. The Modular Exponentiation architecture is designed based on the above full adders and is simulated and synthesized using Xilinx Vivado Zynq-7000 family configurable device. From the synthesis results, the dynamic power dissipation, Figure of Merit (FOM), and Energy Delay Product (EDP) of the ANN Modular Exponentiation circuit shows an improvement compared to other designs. The total power consumption, dynamic power dissipation, FOM, and EDP of ANN Full Adder and Modular Exponentiation circuit can achieve (8%, 16%), (23.5%, 20.7%), (14.7%, 14%), and (28.5%, 16%) compared to RLG Full adder and Modular Exponentiation circuit.KeywordsFeynman gateMLPerceptronSwitching activityPDPModular multiplierToffoli gate

We discuss a VLSI electronic neuron circuit that implements the Hindmarsh and Rose neuron model. Magnitude and time scaling techniques are employed for a 2 V power supply operation. A subthreshold operation technique and a single MOS resistor are used to minimize area and power consumption. Output bursts of the electronic neuron can be modulated dynamically by varying the input voltage level. The circuit is designed using a 0.25 /spl mu/m CMOS standard process, and the total power dissipation is 163.4 /spl mu/watt.

Thermal analysis has long been essential for designing reliable, high-performance, cost-effective integrated circuits (ICs). Increasing power densities are making this problem more important. Characterizing the thermal profile of an IC quickly enough to allow feedback on the thermal effects of tentative design changes is a daunting problem, and its complexity is increasing. The move to nanoscale fabrication processes is increasing the importance of quantum thermal phenomena such as ballistic phonon transport. Accurate thermal analysis of nanoscale ICs containing hundreds of millions of devices requires characterization of thermal effects on length scales that vary by several orders of magnitude, from nanoscale quantum thermal effects to centimeter-scale cooling package impact. Existing chip.package thermal analysis methods based on classical Fourier heat transfer cannot capture nanoscale quantum thermal effects. However, accurate device-level modeling techniques, such as molecular dynamics methods, are far too slow for use in full-chip IC thermal analysis. In this work, we propose and develop ThermalScope, a multi-scale thermal analysis method for nanoscale IC design. It unifies microscopic and macroscopic thermal physics modeling methods, i.e., the Fourier and Boltzmann transport modeling methods. Moreover, it supports adaptive multi-resolution modeling. Together, these ideas enable efficient and accurate characterization of nanoscale quantum heat transport as well as chip.package level heat flow. ThermalScope is designed for full-chip thermal analysis of billion-transistor nanoscale IC designs, with accuracy at the scale of individual devices. ThermalScope enables accurate characterization of temperature-related effects, such as variation in leakage power and delay. ThermalScope has been implemented in software and used for full-chip thermal analysis and temperature-dependent leakage analysis of an IC design with more than 150 million transistors. It will be publicly released for free academic and personal use.

Transistor aging is a major reliability concern for nanoscale CMOS technology that can significantly reduce the operation lifetime of very large-scale integration chips. Negative bias temperature instability (NBTI) is a major contributor to transistor aging that affects pMOS transistors. On the other hand, leakage power is becoming a dominant factor of the total power with successive technology scaling. Since the input combinations applied to a logic core have a significant impact on both NBTI and leakage power, input vector control can be used to optimize both phenomena during idle cycles. In this paper, we present an efficient input vector selection technique based on linear programming for cooptimizing the NBTI-induced delay degradation and leakage power consumption during standby mode. Since the NBTI-induced delay degradation and leakage power are not affected by the input vector in the same direction, we provide a pareto curve based on both phenomena. A suitable point from such a pareto curve is chosen based on circuit conditions and requirements during runtime.

Evaluation of variability using Schmitt trigger on full adders layout

A Novel high-speed low power 9T full adder

A systematic review on full adder designs in Quantum-dot Cellular Automata

Full adder and full subtractor are often a combinational logic circuit that performs three one-bit binary digits of addition and subtraction operations, respectively. Full adder is an important element for the development of different devices such as microprocessors and digital signal processors. The design of the area-efficient full adder is essential to build an area-efficient processor. In this paper, we have implemented an area-efficient full adder circuit and full subtractor circuit using quantum dot cellular automata (QCA). A better EX-OR gate configuration in terms of efficient area is chosen to create the full adder and full subtractor designs. The proposed full subtractor and full adder architecture requires 22 and 23 quantum cells, respectively, whose effective area is 0.0192 μm2 (micro-metre square) only. A tool called QCADesigner is used to implement the design and check its performance. The dissipation of energy is measured using the QCAD-E tool.KeywordsComplementary metal–oxide–semiconductor (CMOS) technologyExclusive-OR (EX-OR) gateFull adder (FA)Full subtractor (FS)Quantum dot cellular automata (QCA)QCADesigner

This paper, proposed a hybrid full adder with low power and less area using 8 transistors. Majority not gate and GDI techniques are collectively used for design this hybrid full adder. Some beforehand composed cells endure from non-full swing output, low speed, and high power utilization issues. While the new full adder has insignificant range overhead, it has enhanced the power Utilization of the circuit when contrasted with other full adder circuit. We have verified this full adder by utilizing cadence virtuoso gpdk 180nm technology at 1.2V supply voltage.

The subthreshold and gate oxide leakage power characteristics of domino logic circuits are evaluated in this paper. The preferred input vectors and node voltage states are identified to minimize the total leakage power consumption in the sleep mode. New low leakage design guidelines based on the results are presented. Previous studies indicate that a discharged dynamic node voltage state with high inputs is preferable to reduce the subthreshold leakage power consumption in an idle dual threshold voltage domino gate. However, the gate oxide leakage is ignored in the previous studies. The significantly increased gate dielectric tunneling current, as described in this paper, shifts the leakage power characteristics of dynamic circuits in the sub-65nm CMOS technologies. Contrary to the previously published techniques in older technologies, a charged dynamic node voltage state with low inputs is preferred for reducing the total leakage power consumption in the wide fan-in dual threshold voltage domino gates. Similarly, a charged dynamic node voltage state with low inputs is preferred for lowering the leakage power consumption in all types of low threshold voltage domino gates in a 45nm CMOS technology

New designs of Redundant Binary full Adders are proposed for redundant binary system, and implemented using 0.18 mum CMOS technology. The proposed full adder designs require low number of transistors and show lower power dissipation and reduced time delay compared to currently available designs. These new designs can be widely used for computer arithmetic units in redundant binary systems. As case studies, two efficient on-line multipliers are implemented using the new full adders, providing improved performance while requiring lower number of transistors.