Let's study whole-program cache behaviour analytically

Trace based cache simulation are common techniques in design space exploration. In this paper, we develop an efficient strategy to simulate cache behavior for affine computations. Our framework exploits the regularity of polyhedral programs to implement a cache set partition transformation to parallelize both trace generation and simulation. We demonstrate that our framework accurately models the cache behavior of polyhedral programs while achieving significant improvements in simulation time. Extensive evaluations show that our proposed framework systematically outperforms the time-partition based parallel cache simulation.

Improving data locality in programs which manipulate arrays has been the subject of a great deal of research. Much of the work on improving data locality examines individual loop nests; other work includes transformations such as loop fusion, which combines loops so that multiple loop nests can be transformed as a single loop nest. We propose a data-driven method to optimize locality across multiple loop nests. Our technique achieves loop fusion-like results even when normal loop fusion is illegal without enabling transformations. Given an array whose locality should be optimized, it also finds other calculations that can profitably be executed with the computation of that array.KeywordsTransitive ClosureArray ElementIteration SpaceLoop NestInnermost LoopThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Affine loop transformations have often been used for program optimization. Usually their focus lies on single loop nests. A few recent approaches also handle global programs with multiple loop nests but they are not really scalable towards realistic applications with dozens of nests. To reduce complexity, we split affine transformations into a linear transformation step and a translation step. This translation step can be used to perform general multidimensional loop fusion. We show that loop fusion can be performed incrementally and provide a greedy algorithm, which we illustrate on a simple example. Finally, we present a heuristic for data locality and provide some experimental results.

In time-parallel simulation, the simulation time axis is decomposed into a number of slices which are assigned to parallel processes for concurrent simulation. Although a promising parallelization technique, it is difficult to be applied. Recently, using approximation with time-parallel simulation has been proposed to extend the class of suitable models and to improve the performance of existing models. In trace-driven cache simulation, sequences of memory requests are processed to determine the performance of variously sized caches. Time-parallel simulation has been applied to trace-driven cache simulation, but only with limited scalability of the parallel algorithm. In order to solve the scaling problem, this work uses approximation with time-parallel cache simulation. Although introducing an uncertainty in the results, the approximate algorithms work in a way that result accuracy increases monotonically with time, allowing a direct control of the quality of results. Experiments with a prototypical implementation indicate the viability of this approach.

This paper presents an approach advocating abstract clocks to represent data-intensive applications executed on multiprocessor systems-on-chip (MPSoCs) for facilitating the exploration of large design spaces. By using abstract clocks, the advocated method characterizes applications defined by multiple loop nests, as well as, useful loop transformations that contribute to an efficient application execution. It combines the advantages of optimizations provided by loop transformations and the precision of information on scheduling captured by the abstract clocks. As a result, it favors a rapid, and yet accurate design space exploration (DSE) of data-intensive systems.

Observation-based slicing is a recently-introduced, language-independent slicing technique based on the dependencies observable from program behaviour. Due to the well-known limits of dynamic analysis, we may only compute an under-approximation of the true observation-based slice. However, because the observation-based slice captures all possible dependence that can be observed, even such approximations can yield insight into the limitations of static slicing. For example, a static slice, S, that is strictly smaller than the corresponding observation based slice is potentially unsafe. We present the results of three sets of experiments on 12 different programs, including benchmarks and larger programs, which investigate the relationship between static and observation-based slicing. We show that, in extreme cases, observation-based slices can find the true minimal static slice, where static techniques cannot. For more typical cases, our results illustrate the potential for observation-based slicing to highlight limitations in static slicers. Finally, we report on the sensitivity of observation-based slicing to test quality.

In this article we describe a memory tracing and profiling tool called Gleipnir. Gleipnir is a plug-in tool for a widely used binary instrumentation framework, Valgrind. Gleipnir's ability to collect fine grained memory traces and associate each access to source level data structures and elements of these structures, makes it a good candidate tool for advanced memory analysis and studying complex memory access patterns. The data provided by Gleipnir may be used by cache simulators to analyze accesses to data structure elements and understand the dynamic memory behavior of programs. The goal of Gleipnir is to give the programmer aid in refactoring data and code. In addition to Gleipnir we introduce a cache simulation tool, Gl cSim. Gl cSim is an extension to DineroIV (a uni-processor simulator) that tracks Gleipnir provided trace and debug-information.

As program behavior becomes complex, it’s increasingly important to analyze their behavior statistically. The article describes two separate but synergistic tools for statistically analyzing large Lisp programs. The first tool, called CLIP (Common Lisp Instrumentation Package), allows the researcher to define and run experiments, including experimental conditions (parameter values of the planner or simulator) and data to be collected. The data are written out to data files that can be analyzed by statistics software. The second tool, called CLASP (Common Lisp Analytical Statistics Package), allows the researcher to analyze data from experiments by using graphics, statistical tests, and various kinds of data manipulation. CLASP has a graphical user interface (using CLIM, the Common Lisp Interface Manager) and also allows data to be directly processed by Lisp functions. Finally, the paper describes a number of other data-analysis modules that have been added to work with CLIP and CLASP.

Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip area. Simulation, in particular trace-driven simulation, is widely used to estimate cache hit rates. However, simulation is too slow to be deployed in design space exploration, especially when there are hundreds of design points and the traces are huge. In this article, we propose a novel analytical approach for design space exploration of instruction caches. Given the program control flow graph (CFG) annotated only with basic block and control flow edge execution counts, we first model the cache states at each point of the CFG in a probabilistic manner. Then, we exploit the structural similarities among related cache configurations to estimate the cache hit rates for multiple cache configurations in one pass. Experimental results indicate that our analysis is 28--2,500 times faster compared to the fastest known cache simulator while maintaining high accuracy (0.2% average error) in estimating cache hit rates for a large set of popular benchmarks. Moreover, compared to a state-of-the-art cache design space exploration technique, our approach achieves 304--8,086 times speedup and saves up to 62% (average 7%) energy for the evaluated benchmarks.

This paper presents a new integrated compiler framework for improving the cache performance of scientific applications. In addition to applying loop transformations, the method includes data layout optimizations, i.e., those that change the memory layouts of data structures (arrays in this case). A key characteristic of this approach is that loop transformations are used to improve temporal locality while data layout optimizations are used to improve spatial locality. This optimization framework was used with sixteen loop nests from several benchmarks and math libraries, and the performance was measured using a cache simulator in addition to using a single node of the SGI Origin 2000 distributed-shared-memory machine for measuring actual execution times. The results demonstrate that this approach is very effective in improving locality and outperforms current solutions that use either loop or data transformations alone. We expect that our solution will also enable better register usage due to increased temporal locality in the innermost loop, and that it will help in eliminating false-sharing on multiprocessors due to exploiting spatial locality in the innermost loop.

Soft errors and energy consumption have both become the major design concerns for microprocessors, as a result of increasing transistor counts, shrinking feature size, lowering supply voltages. As the largest on-chip structures, cache memories face more serious reliability and energy challenges. The awareness of reliable energy-efficiency is greatly helpful to achieve a tradeoff between reliability and energy consumption with minimum costs for cache. In this paper, a new metric, MOPUETF (Mean Operations Per Unit Energy To Failures), is proposed to characterize the cache behavior in terms of reliable energy-efficiency. We compare three different metrics and MOPUETF is demonstrated to be more suitable for reliable energy-efficiency evaluation of cache. We also conduct a comprehensive characterization of dynamic behavior of Level-1 data cache (LID) MOPUETF. Experimental results show that LID MOPUETF exhibits different degree of variance for different programs, and fuzzy correlation exists between LID MOPUETF and several measurable performance metrics of processors. The dynamic reliable energy-efficient behavior of cache could be accurately captured in a larger space of performance metrics.

There are important classes of programming errors that are hard to diagnose, both manually and automatically, because they involve a program's dynamic behavior. This article describes a compile-time analyzer that detects these dynamic errors in large, real-world programs. The analyzer traces execution paths through the source code, modeling memory and reporting inconsistencies. In addition to avoiding false paths through the program, this approach provides valuable contextual information to the programmer who needs to understand and repair the defects. Automatically-created models, abstracting the behavior of individual functions, allow inter-procedural defects to be detected efficiently. A product built on these techniques has been used effectively on several large commercial programs. Copyright © 2000 John Wiley & Sons, Ltd.

Gravitational waves were predicted by Albert Einstein more than a century ago, but only in 2015, the Laser Interferometer Gravitational-Wave Observatory (LIGO) was able to detect them. The gravitational wave phenomenon can be compared to spreading water from a lake after a stone has been thrown into it. Here, gravitational wave generation comes from an astronomical binary system formed by black holes or neutron stars. However, unlike the water, the amplitude of those gravitational waves is on a scale smaller than a proton’s size. Despite this, we can describe it with simple equations in a phenomenological way. We can model those waves on a regular computer using post Newtonian physics. Here we were able to generate gravitational waves from computational simulations and make its data analyze. When a gravitational wave is detected in the real-world problem, there is a great interest in establishing the physical features of the astronomical bodies involved in the process. In this way, we propose applying a simple neural network to receive the gravitational wave data and infer information about the astronomical bodies’ mass. The experimental results show that a simple neural network can extract mass information from the gravitational wave data. The recognition process proposed is much more straightforward than the complex computation based on numerical relativity for gravitational wave data analysis.

With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective way to exploit the data locality. Traditional loop partition techniques, however, consider only a singleton nested loop. This paper presents multiple loop partition scheduling technique, which combines the loop partition and data padding to generate the detailed partition schedule. The computation and data prefetching are balanced in the partition schedule, such that the long memory latency can be hidden efficiently. Multiple loop partition scheduling explores parallelism among computations, and exploit the data locality between different loop nests as well in each loop nest. Data padding is applied in our technique to eliminate the cache interference, which overcomes the problem of cache conflict misses arisen from loop partition. Therefore, our technique can be applied in architectures with low associativity cache. The experiments show that multiple loop partition scheduling can achieve the significant improvement over the existing methods

This paper presents a hybrid cache analysis for the simulation-based evaluation of data caches in embedded systems. The proposed technique uses static analyses at the machine code level to obtain information about the control flow of a program and the memory accesses contained in it. Using the result of these analyses, a high-speed source-level simulation model is generated from the source code of the application, enabling a fast and accurate evaluation of its data cache behavior. As memory accesses are obtained from the binary-level control flow, which is simulated in parallel to the original functionality of the software, even complex compiler optimizations can be modeled accurately. Experimental results show that the presented source-level approach estimates the cache behavior of a program within the same level of accuracy as established techniques working at the machine code level.