LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

This paper presents a low hardware overhead test pattern generator (TPG) for scan-based BIST that can reduce switching activity in CUTs during BIST and also achieve very high fault coverage with a reasonable length of test sequence. Since the correlation between consecutive vectors applied to a circuit during BIST is significantly lower, switching activity in the circuit can be significantly higher during BIST than that during its normal operation. Excessive switching activity during test application can damage CUTs during BIST. The proposed BIST decreases the number of transitions that occur at scan inputs during scan shift operations and hence decreases switching activity during BIST. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST TPG, both of which are proposed in previous publications. This paper shows that the 3-weight WRBIST TPG, which is used to detect random pattern resistant faults, can also be used to reduce switching activity in CUTs during BIST. Experimental results also show that the proposed BIST can be implemented with very low area overhead.

As the technology is changing at grater pace there is a necessity to develop the devices that are efficient with respect to area and power. This paper presents a hybrid type BIST TPG which is efficient with respect to power and area. The proposed BIST TPG comprises of two types of BIST TPG's one is Modified Low Transition Random Test Pattern Generator (MLRTPG) and the other is Adder based 3-Weighted Random Test Pattern Generator (A3WRTPG). The MLRTPG aims at reducing power dissipation during BIST activity where as A3WRTPG aims at reducing the area overhead and improving the fault coverage of the BIST TPG. The MLRTPG achieves power dissipation by reducing the transitions that are associated with Circuit under Test (CUT) during BIST operation. The A3WRTPG aims at reducing the area overhead by employing Adders and D-flip flops to alter the weights of weighted deterministic BIST TPG to achieve improvement in detection probabilities of BIST TPG to detect Random Pattern Resistant Faults. The testing of proposed BIST TPG is carried under two phases. The first phase of testing is carried out by MLRTPG to detect easy-to-detect faults and the second phase of testing is carried out A3WRTPG to detect the faults that are dropped out by MLRTPG. The reduction of power and area of proposed BIST TPG also achieves significant improvement in parasitic capacitance which is the major dominating source of different circuit parameters.

Design for low power testing is primary concern in modern VLSI circuits. In this paper a novel test pattern generator (TPG) is proposed which is more suitable for built in self test (BIST) architecture, used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption during testing of VLSI circuits. In CMOS devices 80% of power consumption is due to switching activity occurred during operation. The proposed TPG is based on read only memory (ROM) which is carefully designed to store the test vectors with minimum area over the conventional ROM. This reduces the number of CMOS transistors significantly when compared to that of LFSR/counter TPG. The proposed TPG is more suitable for deterministic pattern testing and the fault coverage is improved over the LFSR. Low power reordered test patterns also can also be stored in the same order to reduce the test power in circuit under test (CUT). The TPG is designed and implemented for benchmark circuits ISCAS 85 and 89. Experimental results shows that a considerable reduction in number of CMOS devices and test power is achieved over the LFSR-TPG

In this paper, a vector-less simple technique based on the oscillation-test strategy (OTS) is proposed for the test of the Buck regulator. In the test mode, the circuit under test (CUT) of the buck regulator could be easily transformed into an oscillator for generating the oscillating signal. By observing the frequency and amplitude of the oscillating signal, we could detect the CUT to see if it is faulty or fault-free. Simulation results show that the fault coverage for hard faults could reach up to 99%. Based on the facts of the simple structure and high fault coverage, OTS is considered as a useful technique in the testing of the Buck regulator.

This paper presents three built-in self-test (BIST) schemes for robust testing of stuck-open faults in combinational FCMOS complex cells of arbitrary structure. The first method shows that all single stuck-open faults can be robustly tested by applying a universal sequence of 5/spl times/2/sup n/ vectors to the modified circuit under test (CUT), and counting the number of 1's in the output response. The second method uses the same test pattern generator (TPG), but faults are detected by a self comparison technique without the need of storing a signature. Finally, we propose a new adaptive BIST technique, where the TPG is driven by the past outputs of the CUT itself In all the cases, the TPG is universal, i.e., if does not depend on the functionality and the structure of the CUT, but does ensure robust testing. Neither any test vector, nor any fault dictionary, is required. These approaches provide simplicity, less testing time and test data, and compare favorably with earlier BIST designs for CMOS circuits.

A new and effective pseudorandom test pattern generator, termed GLFSR, is introduced. The test pattern generation by GLFSR achieves a higher degree of randomness. Experimental results on common benchmark CUT demonstrate that the fault coverage of the propose pattern generator is significantly higher compared to conventional pattern generation techniques. For Cutpsilas stuck-at fault and transition faults, test pattern generator using GLFSR can attain equivalent fault coverage but fewer patterns than LFSR pattern generator. GLFSR can be used as test pattern for the architecture of BIST.

Single input change (SIC) test sequence has been investigated in recent years because it is effective to reduce the test power consumption. Deterministic built-in self-test (BIST) can achieve the high fault coverage with relatively short test application time and low test cost. In this paper, seeds selection scheme of SIC sequences based on deterministic ATPG test patterns is proposed for decreasing the test power consumption and test application time with high test fault coverage. Proper selection of SIC seeds is the key aspect to a successful low power deterministic BIST technique. Furthermore, simulated annealing algorithm is used to optimize the numbers of seeds. A simple hardware structure can implement the generation of SIC sequences. Experimental results based on ISCAS'85 benchmark circuits demonstrate that the proposed algorithm can reduce the number of SIC seeds. Test application time and average power can be decreased, and test fault coverage also keep high compared to random SIC (RSIC) test sequences.

Proposes a new easily testable PLA. In the design process the authors use a simple property of relatively prime numbers. The PLA can be efficiently integrated with random pattern techniques used for testing combinational circuits. In the proposed implementation, test pattern generation and test response compaction are performed by circular self-test path (circular BIST). Very high fault coverage can be achieved in a feasible testing time. >

The area overhead and performance degradation associated with the hardware used to make a circuit testable using the conventional BILBO methodology can often be excessive. This paper presents a new BILBO-oriented methodology, called Built-In test for Balanced Structure (BIBS), that significantly reduces the number of BILBO registers used in creating a testable circuit, and thus decreases the area overhead and performance degradation. The concept of k-step functionally testable circuits is introduced. When the BIBS methodology is employed, circuits under test are guaranteed to be 1-step functionally testable and thus a high fault coverage can be achieved. A novel test pattern generator design to achieve 1-step functional testability for the BIBS TDM is presented. >

Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs. >

This paper presents a smoothing technique for the output sequence of linear feedback shift registers (LFSR) to reduce power consumption in test-per-scan built-in self-test (BIST) applications. The proposed smoother is implemented by adding one multiplexer between the LFSR and scan-chain input of a single scan-chain. The size of the multiplexer is determined the desired smoothing degree. When the smoothed sequence of the LFSR is used to feed the test patterns in test-per-scan BIST, it reduces the number of transitions that occur at scan-chain input during scan shift operations by 25% to 50% depending on the smoothing degree, and hence reduces switching activity in the circuit-under-test (CUT) during test application. The proposed technique can be extended to multiple scan-chains BIST, also to test-per-clock applications. Various properties of the proposed technique and the methodology of the design are presented in this paper. Experimental results for the ISCAS'89 benchmark circuits show that the proposed design can reduce the switching activity up to 55% with a negligible effect on the fault coverage and test application time.

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit. Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length, compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length, the memory requirements during the test application and the test application time are reduced. Secondly, the extent of test compaction possible for deterministic test sequences indicates that test pattern generators spend a significant amount of time generating test vectors that are not necessary. The compacted test sequences provide a target for more efficient deterministic test generators. Two types of compaction techniques exist: dynamic and static. The dynamic test sequence compaction performs compaction concurrently with the test generation process and often requires modification of the test generator. The static test sequence compaction is done in a post-processing step to the test generation and is independent of the test generation algorithm and process. In the thesis, a new idea for static compaction of test sequences for synchronous sequential circuits has been proposed. Our new method - SUSEM (Set Up Sequence Elimination Method) uses the circuit state information to eliminate some setup sequences for the target faults and consequently reduce the test sequence length. The technique has been used for the test sequences generated by HITEC test generator. ISCAS89 benchmark circuits were used in our experiments, for some circuits which have a large number of target faults and relatively small number of flip-flops, the very significant compactions have been obtained. The more important is that this method can be used to improve the test generation procedure unlike most static compaction methods which blindly or randomly remove parts of test vectors and cannot be used to improve the test generators.

We describe a new approach to test generation for stuck-at faults in synchronous sequential circuits. Under this approach, the input vectors comprising the test sequence are fixed in advance. The process of generating the test sequence consists of ordering the precomputed input vectors such that the resulting test sequence has as high a fault coverage as possible. The advantage of this approach is that its computational complexity is limited by limiting the search space to a given set of input vectors and a given test sequence length. We describe a specific implementation of this approach. Experimental results demonstrate that restricting the search space to a fixed number of precomputed input vectors is sufficient for achieving the highest known fault coverage, or a fault coverage close to it, for benchmark circuits.

A logic fault test simulation environment for core-based digital systems is proposed in this paper. The simulation environment emulates a typical built-in self-test (BIST) environment with test pattern generator that sends its outputs to a circuit under test (CUT) and the output streams from the CUT are fed into a response data analyzer. The developed simulator is suitable for testing digital IP cores. The paper describes in details the test architecture and application of the logic fault simulator. Some partial simulation results on ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits are provided.

Star test is a novel test pattern generation technique in which a few test vectors serve as centers of clusters for other test vectors which are derived by complementing at random their coordinates. By properly selecting the deterministic patterns as centers, the star tests have very high probability to detect most of the faults in a circuit. This paper presents an efficient algorithm to combine the star test approach with a traditional test pattern generator yielding a significant speed up of the ATPG process. With the new STAR-ATPG methodology, the major effort of the test generation is transferred from an computationally more complex test pattern generation process into simpler fault simulation. Experimental results on several large industrial designs demonstrate that a factor of 1.5-2.5 average speed up is achieved by the new method with the same abort limit. Also, STAR-ATPG achieves higher fault coverage than traditional ATPG under the same abort limit. To achieve the same fault coverage as STAR-ATPG, it requires the traditional method to increase the abort limit significantly and result in 5 times slower.