Logic fault test simulation environment for IP core-based digital systems

This paper proposes a Verilog HDL-based fault simulation and testing environment for embedded IP core-based digital systems, specifically targeted towards synchronous memory-based systems, for detecting single stuck-line faults. The simulator emulates a typical BIST (built-in self-testing) environment with test pattern generator that sends its outputs to a MUT (module under test) and the output streams from the MUT are fed into a response data analyzer. A fault is detected if the module response is different from that of the fault-free module. All of the faults detected are recorded in a detailed simulation results file. The fault simulator is suitable for testing sequential circuits described in Verilog HDL. The automatic fault simulator generates tests for the MUT described at the gate and flip-flop level. There are very few constraints on the circuit. The simulation process is completely automatic, and requires no intervention from the designer during the test generation process. The paper describes in detail the architecture and applications of the fault simulator along with the models of sequential elements used. Results on some simulation experiments on ISCAS 89 sequential benchmark circuits are also provided.

This paper presents three built-in self-test (BIST) schemes for robust testing of stuck-open faults in combinational FCMOS complex cells of arbitrary structure. The first method shows that all single stuck-open faults can be robustly tested by applying a universal sequence of 5/spl times/2/sup n/ vectors to the modified circuit under test (CUT), and counting the number of 1's in the output response. The second method uses the same test pattern generator (TPG), but faults are detected by a self comparison technique without the need of storing a signature. Finally, we propose a new adaptive BIST technique, where the TPG is driven by the past outputs of the CUT itself In all the cases, the TPG is universal, i.e., if does not depend on the functionality and the structure of the CUT, but does ensure robust testing. Neither any test vector, nor any fault dictionary, is required. These approaches provide simplicity, less testing time and test data, and compare favorably with earlier BIST designs for CMOS circuits.

Design for low power testing is primary concern in modern VLSI circuits. In this paper a novel test pattern generator (TPG) is proposed which is more suitable for built in self test (BIST) architecture, used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption during testing of VLSI circuits. In CMOS devices 80% of power consumption is due to switching activity occurred during operation. The proposed TPG is based on read only memory (ROM) which is carefully designed to store the test vectors with minimum area over the conventional ROM. This reduces the number of CMOS transistors significantly when compared to that of LFSR/counter TPG. The proposed TPG is more suitable for deterministic pattern testing and the fault coverage is improved over the LFSR. Low power reordered test patterns also can also be stored in the same order to reduce the test power in circuit under test (CUT). The TPG is designed and implemented for benchmark circuits ISCAS 85 and 89. Experimental results shows that a considerable reduction in number of CMOS devices and test power is achieved over the LFSR-TPG

The technique of Test Sequence Generation (TSG) plays a key role in Built-In Self-Test (BIST) architecture implementation. Major problem with any test sequence generator is to produce long, unpredictable key sequences which can be applied to Circuit Under Test (CUT) in order to detect the faults efficiently. Digital Systems/Circuits are tested by inducing appropriate stimuli and checking the responses generated. Generation of such stimuli together with calculation of their anticipated responses is called Test Sequence Generation or Test Pattern Generation. Due to certain limitations of Automatic Test Equipment (ATE), there exist methods where the main functions of the external tester have been moved onto the chip, Such DFT practice is generally known as BIST. With the progression of test technology, various techniques have been developed for IC testing. This paper presents three techniques: Cellular Automata (CA), Linear Feedback Shift Register (LFSR), and Single Bit Change Sequence Generator (SBCSG), used for test pattern generation and test response analysis in a typical BIST circuit. All the three TPGs are analyzed with respect to the parameters like Power, Time and Area to demonstrate their shortfalls and suitability for intended application.

According to Moore's law, the number of transistors in a chip doubles every eighteen months. Since, the number of transistors is increasing, the probability of finding a fault in the transistors also increases. In order to detect the faults and to avoid potential faults, testing is necessary. In this paper, a power efficient Built-In-Self-Test (BIST) is designed using bit-swapping LFSR and a modified MISR for testing a combinational circuit. The Bit-swapping LFSR is used as the Test Pattern Generator (TPG) and the modified MISR is used as the Output Response Analyzer (ORA). The TPG produces the test patterns, which is given as inputs to the Circuit Under Test (CUT). The ORA analyzes the outputs of the CUT and a pass/fail signal is generated which indicates whether there are any faults in the circuit. This BIST architecture can detect single stuck-at faults present in a combinational circuit. The results were simulated in Xilinx ISE Design Suite 14.4 using VHDL and synthesized in Vivado 2018.2.

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

This paper presents a low hardware overhead scan-based test pattern generator (TPG) that can reduce switching activity in circuit under test (CUT) during test and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed TPG is comprised of two TPGs: Seed selected Random Test Pattern Generator (RTPG) and 3-weight Weighted Random Built-in-Self Test (WRBIST). Test pattern generated by seed selected RTPG detect easy-to-detect faults and test pattern generated by 3-weight WRBIST detect hard faults that remain undetected after seed selected RTPG patterns are applied. Experimental results show that the proposed TPG schemes can attain 100% fault coverage for all benchmark circuits with drastically reduced test sequence lengths. This reduction in test sequence length achieved at low hardware cost even for benchmark circuits that have large number of scan inputs.

Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs. >

A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (/spl les/2/sup 30/) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%.

With the increasing complexity of modern VLSI circuits, achieving high quality built-in self-test requires monitoring an increasingly large number of internal nodes. Due to the limitations in observing large numbers of nodes, it has become increasingly necessary to compact the output from a large number of lines to a small number of lines in a process known as space compaction. In the past, space compaction has usually been performed by circuit-independent compactors, such as the popular parity function. Recently, a class of circuit-specific space compactors, known as programmable space compactors (PSCs), has been proposed. A PSC is a highly effective space compactor tailored for a specific circuit under test (CUT) subjected to a specific set of test stimuli. Circuit-specific information such as the fault-free and expected faulty behaviour of a circuit can be used to choose compactors which have better fault coverage and/or lower area costs than the parity function. The drawback of PSCs is the difficulty involved in finding optimal PSCs for a circuit. The space of possible PSC functions is extremely large and grows exponentially with the number of lines to be compacted. Although searching for optimal PSC functions is a difficult problem, it is not impossible. This thesis presents a method for searching for combinational PSCs based upon genetic algorithms (GAs), a randomized search technique. Randomized search techniques, such as simulated annealing and genetic algorithms, have become increasingly popular in recent years as methods for solving search and optimization problems beyond the capabilities of classical techniques. This thesis develops a procedure for using circuit-specific information in the application of (GAs) to the search for optimal PSCs for a given CUT and a given set of test stimuli. A measure of the effectiveness, or fitness, of PSCs is developed as a means for guiding the genetic search. The factors used to assess the effectiveness of a PSC are its

Safety-critical systems embedding concurrent on-line testing techniques are vulnerable to design issues causing the degradation of totally self-checking (TSC) property, which is proved to be fatal for further operations (e.g., space electronics, medical devices). In addition to the exploration of the degradation of TSC property over time, a concurrent on-line testing architecture is offered that adjusts the input activity, addressing the absence of input values or the low frequency of their appearance (e.g., during sleep mode). During concurrent on-line testing, the inputs of the circuit under test (CUT) are, at the same time, its test vectors. This architecture tolerates possible degradation of the terms that contribute to the calculation of the totally self-checking goal (TSCG(t)). An adaptive built-in self-test (BIST) unit is proposed that dynamically applies test vector subsets when permitted, based on the frequency of appearance of the input values. The clustering of the inputs is based on the k-means algorithm and, in combination with the ordering of the test vectors to minimize the subsets, results in partitioning the test procedure in a significantly shorter time. The comparison to other solutions used for concurrent on-line testing showed that the proposed adaptive BIST has significant advantages. It can cope with rare occurrences, or even no occurrence, of input values by enabling the BIST mechanism appropriately. The results showed that it may increase the TSCG(t) up to almost 90% when applied during a low-power mode and present better concurrent test latency (CTL) when assumptions regarding the availability of all input values and the probability of occurrence are not realistic.

We address test data compaction for built-in self-test (BIST). The thrust of the work focuses on BIST space compaction, a process increasingly required when a large number of internal circuit nodes need to be monitored during test but where area limitations preclude the association of observation latches for all the monitored nodes. We introduce a general class of space compactors denoted as programmable space compactors (PSCs). Programmability enables highly-effective space compactors to be designed for circuits under test (CUT) subjected to a specific set or test patterns. Circuit-specific information such as the fault-free and expected faulty behavior of a circuit are used to choose PSCs that have better fault coverage and/or lower area costs than the commonly-used parity function. Finding optimal PSCs is a difficult task since the space of possible PSC functions is extremely large and grows exponentially with the number of lines (nodes) to be compacted. We describe an optimization search method based on genetic algorithms for finding combinational PSCs. The factors used to assess the effectiveness of a PSC are its fault coverage and implementation area.

The paper presents a built-in self-testing (BIST) technique for leakage monitoring using a time-based bootstrapped sensor at near-threshold supply. In order to observe critical leakage behavior in near-threshold systems, the BIST circuit duplicates the leakage current and a leakage quantizer converts the sensed current into digital outputs. Moreover, a bootstrapped ring oscillator (BTRO) serves as an ultra low-voltage sensor to operate even in deep sub-threshold region. It suppresses most of the leakage current and has high energy efficiency to convert sensed leakage current to oscillation frequency. As a result, it monitors leakage current from the circuit under test (CUT) and quantizes the leakage to high resolution digital outputs. In addition, our design also can be used to monitor the process variation in the ultra low-voltage application. The design and test technique is simulated in 90 nm 1P9M SPRVT CMOS process. As compared to state-of-art works, the proposed sensor can operate even at 0.2 to 0.4V VDD in different corners. Besides, it achieves 11-bit resolution under 10us testing time.

As the technology is changing at grater pace there is a necessity to develop the devices that are efficient with respect to area and power. This paper presents a hybrid type BIST TPG which is efficient with respect to power and area. The proposed BIST TPG comprises of two types of BIST TPG's one is Modified Low Transition Random Test Pattern Generator (MLRTPG) and the other is Adder based 3-Weighted Random Test Pattern Generator (A3WRTPG). The MLRTPG aims at reducing power dissipation during BIST activity where as A3WRTPG aims at reducing the area overhead and improving the fault coverage of the BIST TPG. The MLRTPG achieves power dissipation by reducing the transitions that are associated with Circuit under Test (CUT) during BIST operation. The A3WRTPG aims at reducing the area overhead by employing Adders and D-flip flops to alter the weights of weighted deterministic BIST TPG to achieve improvement in detection probabilities of BIST TPG to detect Random Pattern Resistant Faults. The testing of proposed BIST TPG is carried under two phases. The first phase of testing is carried out by MLRTPG to detect easy-to-detect faults and the second phase of testing is carried out A3WRTPG to detect the faults that are dropped out by MLRTPG. The reduction of power and area of proposed BIST TPG also achieves significant improvement in parasitic capacitance which is the major dominating source of different circuit parameters.

A structure-independent method for space compaction based on a new generic scheme is presented in this paper. The compactor compresses test responses of a circuit-under-test (CUT) to a single periodic data stream with guaranteed zero-aliasing, and can be designed only from the knowledge of the test set and the corresponding fault-free responses. An additional response logic and a special code checker are used to design the compactor. The same test set given for the CUT also detects all multiple stuck-at faults in the response logic, and almost all the faults in the rest of the compactor. Further, time compaction is also easily achieved. Since the design does not need any structural information of the CUT, it is useful for testing embedded cores.