On selecting programmable space compactors for built-in self-text using genetic algorithms

We address test data compaction for built-in self-test (BIST). The thrust of the work focuses on BIST space compaction, a process increasingly required when a large number of internal circuit nodes need to be monitored during test but where area limitations preclude the association of observation latches for all the monitored nodes. We introduce a general class of space compactors denoted as programmable space compactors (PSCs). Programmability enables highly-effective space compactors to be designed for circuits under test (CUT) subjected to a specific set or test patterns. Circuit-specific information such as the fault-free and expected faulty behavior of a circuit are used to choose PSCs that have better fault coverage and/or lower area costs than the commonly-used parity function. Finding optimal PSCs is a difficult task since the space of possible PSC functions is extremely large and grows exponentially with the number of lines (nodes) to be compacted. We describe an optimization search method based on genetic algorithms for finding combinational PSCs. The factors used to assess the effectiveness of a PSC are its fault coverage and implementation area.

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

Design for low power testing is primary concern in modern VLSI circuits. In this paper a novel test pattern generator (TPG) is proposed which is more suitable for built in self test (BIST) architecture, used for testing of VLSI circuits. The objective of the BIST is to reduce power consumption during testing of VLSI circuits. In CMOS devices 80% of power consumption is due to switching activity occurred during operation. The proposed TPG is based on read only memory (ROM) which is carefully designed to store the test vectors with minimum area over the conventional ROM. This reduces the number of CMOS transistors significantly when compared to that of LFSR/counter TPG. The proposed TPG is more suitable for deterministic pattern testing and the fault coverage is improved over the LFSR. Low power reordered test patterns also can also be stored in the same order to reduce the test power in circuit under test (CUT). The TPG is designed and implemented for benchmark circuits ISCAS 85 and 89. Experimental results shows that a considerable reduction in number of CMOS devices and test power is achieved over the LFSR-TPG

This paper presents three built-in self-test (BIST) schemes for robust testing of stuck-open faults in combinational FCMOS complex cells of arbitrary structure. The first method shows that all single stuck-open faults can be robustly tested by applying a universal sequence of 5/spl times/2/sup n/ vectors to the modified circuit under test (CUT), and counting the number of 1's in the output response. The second method uses the same test pattern generator (TPG), but faults are detected by a self comparison technique without the need of storing a signature. Finally, we propose a new adaptive BIST technique, where the TPG is driven by the past outputs of the CUT itself In all the cases, the TPG is universal, i.e., if does not depend on the functionality and the structure of the CUT, but does ensure robust testing. Neither any test vector, nor any fault dictionary, is required. These approaches provide simplicity, less testing time and test data, and compare favorably with earlier BIST designs for CMOS circuits.

This paper presents a smoothing technique for the output sequence of linear feedback shift registers (LFSR) to reduce power consumption in test-per-scan built-in self-test (BIST) applications. The proposed smoother is implemented by adding one multiplexer between the LFSR and scan-chain input of a single scan-chain. The size of the multiplexer is determined the desired smoothing degree. When the smoothed sequence of the LFSR is used to feed the test patterns in test-per-scan BIST, it reduces the number of transitions that occur at scan-chain input during scan shift operations by 25% to 50% depending on the smoothing degree, and hence reduces switching activity in the circuit-under-test (CUT) during test application. The proposed technique can be extended to multiple scan-chains BIST, also to test-per-clock applications. Various properties of the proposed technique and the methodology of the design are presented in this paper. Experimental results for the ISCAS'89 benchmark circuits show that the proposed design can reduce the switching activity up to 55% with a negligible effect on the fault coverage and test application time.

A logic fault test simulation environment for core-based digital systems is proposed in this paper. The simulation environment emulates a typical built-in self-test (BIST) environment with test pattern generator that sends its outputs to a circuit under test (CUT) and the output streams from the CUT are fed into a response data analyzer. The developed simulator is suitable for testing digital IP cores. The paper describes in details the test architecture and application of the logic fault simulator. Some partial simulation results on ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits are provided.

In this paper, a vector-less simple technique based on the oscillation-test strategy (OTS) is proposed for the test of the Buck regulator. In the test mode, the circuit under test (CUT) of the buck regulator could be easily transformed into an oscillator for generating the oscillating signal. By observing the frequency and amplitude of the oscillating signal, we could detect the CUT to see if it is faulty or fault-free. Simulation results show that the fault coverage for hard faults could reach up to 99%. Based on the facts of the simple structure and high fault coverage, OTS is considered as a useful technique in the testing of the Buck regulator.

Mark Watson Morgan Kaufmann Publishers, San Francisco, 1997, 377 pp. ISBN 1-55860-420-0, $44.95 This book is well written and organized to cover how to apply AI (Artificial Intelligence) techniques for practical Internet and Intranet tools by using the Java programming language. In the book, the author uses neural network and genetic algorithms to develop distributed systems that are applied for the Internet and Intranets, such as client/server model and information retrieval tool and so on. Part 1 begins with a good general introduction to AI. The history and survey of Artificial Intelligence research are given briefly. In addition, symbolic processing versus neural networks approaches are discussed. This author opts to use neural network to develop example Internet/Intranet systems in the book. Part 2 consists of Java programs developed for AI, neural networks, genetic algorithms, natural language processing, and expert systems. Chapter 2 illustrates Graphical User Interface (GUI) class that is derived from Applet and Canvas classes in Java, which is used in most example programs in the book. Chapter 3 introduces a frame data structure that is used as a message in distributed systems in the later chapters. Chapter 4 shows neural network classes developed in Java and its theory and implementation. Chapter 5 explains the genetic algorithms and the Java genetic algorithm classes. Chapter 6 describes how to develop and implement natural language processing classes using Java. Chapter 7 shows how to share data objects in distributed systems. For example, distributed AI agent classes are developed to share data objects, WWW data collection agent classes are shown to retrieve documents in the Internet, and small POP (Post Office Protocol) mail classes are developed to send and receive mails. Chapter 8 illustrates how to develop expert systems by using Java Jess, which is based on OPS5/CLIPS expert systems. Part 3 explains how to generate and implement the projects using the Java classes that are developed in Part 2. Chapter 9 shows the project that demonstrates the use of genetic algorithms in chapter 5 to control enemy ships in a scrolling arcade game. Chapter 10 describes the real-time handwriting recognition system developed by using the neural network classes in chapter 4. Chapter 11 illustrates a greedy algorithm to optimize neural networks that is based on the author’s hand-tuning neural training data. Chapter 12 improves neural network training data by applying genetic algorithms, to discard bad training data and to avoid discarding good training data. Chapter 13 describes the distributed natural language processing system that uses natural language processing classes in chapter 6. The data structures in chapter 2 are used to store historical data in a separate server application on any other computer in the Internet or Intranets. The final chapter provides the design and implementation of a complete agent-based information retrieval tool for the Internet. The retrieved documents are stored in ASCII or HTML format. This book is a very good reference book for anyone interested in developing systems using Java in distributed environments, especially applying AI techniques. Also, the author provides the CD-ROM that includes the source code for Java classes developed in the book. Haklin Kimm, University of Tennessee

The role of built in test (BIT) in electronic systems has grown in prominence with the advances in system complexity and concern over maintenance lifecycle costs of large systems. In an environment where standards drive system designs (and provide an avenue for focused advancement in technology), standards for BIT are very much in an evolutionary state. The reasons for advancing the effectiveness of BIT include reduced support overhead, greater, confidence in operation, and increased system availability. The cost of supporting military electronic systems (avionics, communications, and weapons systems) has driven much of the development in BIT technology. But what about the systems that support these end items that contain test and measurement instrumentation - such as automatic test equipment (ATE), simulators and avionics development suites? There has also been a beneficial effect on the maintenance and availability of these systems due to the infusion of BIT into their component assemblies. But the effect has been much more sporadic and fragmented. This paper looks at the state of BIT in test and measurement instruments, explain its affect on system readiness, and present ideas on how to improve BIT technologies and standards. This will not provide definitive answers to BIT development questions, since the factors that affect it are specific to the instrument itself. The topics covered in this paper are: definitions of built-in test, instrument BIT history, importance of BIT fault coverage and isolation in support systems, overview of BIT development process issues that limit the effectiveness of BIT Standards related to instrument BIT, making BIT more effective in support system maintenance and availability and conclusions.

Artificial intelligence and numerical models in hybrid renewable energy systems with fuel cells: Advances and prospects

Problem statement: Spam is an irrelevant or inappropriate message sent on the internet to a large number of newsgroups or users. A spam word is a list of well-known words that often appear in spam mails. Bloom Filter (BF) is used for identification of spam word. Approach: BF is a simple but powerful data structure that can check membership to a static set. The trade-off to use BF is a certain configurable risk of false positives. The odds of a false positive can be made very low if the hash bitmap is sufficiently large. Bin Bloom Filter (BBF) has number of BFs which assign group of words into bins with different false positive rates based on weight of the spam words. Genetic Algorithm (GA) was employed to minimize the total membership invalidation cost of BBF. GA had premature convergence problem. Simulated Annealing (SA) was incorporated with GA to prevent the premature convergence effectively. Results: The experimental results of total membership invalidation cost are analyzed for various sizes of bins. The results showed that the combined GA-SA model outperforms SA and GA model. Conclusion: GA has premature convergence due to its genetic operators that are not able to generate offsprings which are superior to the parents. So more number of similar chromosomes presented on the population. When GA is incorporated with SA new genes were introduced which causes diversity in the population and prevents premature convergence. The combined GA-SA outperforms GA and SA.

Artificial intelligence is a relatively new field of computer science that has evolved rapidly in recent years from the stage of laboratory research to that of the field with various spheres of applications. There is currently a whole set of techniques that allow the construction of programs and artificial intelligence systems, systems considered commercial products, successfully applied in the field of mass production. The purpose of this article is to provide a theoretical picture of the artificial intelligence algorithms used in serial production programming. Current research trends in mass production planning are oriented towards the adoption of hybrid techniques, based on specific algorithms of artificial intelligence, which try to combine the advantages of local search strategies (such as optimization by the ant colony model - Ant Colony Optimization, optimization by the particle set model - Particle Swarm Optimization , Genetic algorithms) with those of global search (such as Simulated annealing), in order to determine those optimal and efficient solutions in the case of mass production scheduling.

Achieving high stable Power Transfer Efficiency (PTE) in Wireless Power Transfer (WPT) systems remains challenging due to the nonlinear, multimodal nature of the optimization space. Conventional algorithms such as Genetic Algorithms (GA), Differential Evolution (DE), and Simulated Annealing (SA) often face premature convergence, sensitivity to parameter settings, and inconsistent performance across runs. To overcome these issues, this study introduces the Evolutionary-Swarm Hybrid Algorithm (ESHA), which integrates DE for directional exploration, GA crossover for population diversity, SA for adaptive convergence, and Lévy Flights for stochastic global search. ESHA was implemented on a WPT system with a fixed 20 cm transmission distance and compared with GA, DE, and SA using three performance indicators: PTE, convergence speed, and computational efficiency. Results show that ESHA achieved a maximum PTE of 97.18%, surpassing GA (96.81%), DE (96.65%), and SA (96.19%), while maintaining zero variance across independent runs. It converged in an average of 31.2 iterations, slightly faster than GA (33.15) and SA (32.1), and comparable to DE (31.3). Execution time was 0.4738 s, close to GA (0.4654 s) and only marginally higher than DE (0.4262 s) and SA (0.4329 s). Statistical validation confirmed significant improvements in PTE (p < 0.05).

Safety-critical systems embedding concurrent on-line testing techniques are vulnerable to design issues causing the degradation of totally self-checking (TSC) property, which is proved to be fatal for further operations (e.g., space electronics, medical devices). In addition to the exploration of the degradation of TSC property over time, a concurrent on-line testing architecture is offered that adjusts the input activity, addressing the absence of input values or the low frequency of their appearance (e.g., during sleep mode). During concurrent on-line testing, the inputs of the circuit under test (CUT) are, at the same time, its test vectors. This architecture tolerates possible degradation of the terms that contribute to the calculation of the totally self-checking goal (TSCG(t)). An adaptive built-in self-test (BIST) unit is proposed that dynamically applies test vector subsets when permitted, based on the frequency of appearance of the input values. The clustering of the inputs is based on the k-means algorithm and, in combination with the ordering of the test vectors to minimize the subsets, results in partitioning the test procedure in a significantly shorter time. The comparison to other solutions used for concurrent on-line testing showed that the proposed adaptive BIST has significant advantages. It can cope with rare occurrences, or even no occurrence, of input values by enabling the BIST mechanism appropriately. The results showed that it may increase the TSCG(t) up to almost 90% when applied during a low-power mode and present better concurrent test latency (CTL) when assumptions regarding the availability of all input values and the probability of occurrence are not realistic.

The technique of Test Sequence Generation (TSG) plays a key role in Built-In Self-Test (BIST) architecture implementation. Major problem with any test sequence generator is to produce long, unpredictable key sequences which can be applied to Circuit Under Test (CUT) in order to detect the faults efficiently. Digital Systems/Circuits are tested by inducing appropriate stimuli and checking the responses generated. Generation of such stimuli together with calculation of their anticipated responses is called Test Sequence Generation or Test Pattern Generation. Due to certain limitations of Automatic Test Equipment (ATE), there exist methods where the main functions of the external tester have been moved onto the chip, Such DFT practice is generally known as BIST. With the progression of test technology, various techniques have been developed for IC testing. This paper presents three techniques: Cellular Automata (CA), Linear Feedback Shift Register (LFSR), and Single Bit Change Sequence Generator (SBCSG), used for test pattern generation and test response analysis in a typical BIST circuit. All the three TPGs are analyzed with respect to the parameters like Power, Time and Area to demonstrate their shortfalls and suitability for intended application.