Lifetime Reliability Aware Architectural Adaptation

As CMOS technology scales down towards nanometer regime and the supply voltage approaches the threshold voltage, increase in operating temperature results in increased circuit current, which in turn reduces circuit propagation delay. This paper exploits this new phenomenon, known as inverse thermal dependence (ITD) for power, performance, and temperature optimization in processor architecture. ITD changes the maximum achievable operating frequency of the processor at high temperatures. Dynamic thermal management techniques such as activity migration, dynamic voltage frequency scaling, and throttling are revisited in this paper, with a focus on the effect of ITD. Results are obtained using the predictive technology models of 7nm, 10nm 14nm and 20nm technology nodes and with extensive architectural and circuit simulations. The results show that based on the design goals, various design corners should be re-investigated for power, performance and energy-efficiency optimization. Architectural simulations for a multi-core processor and across standard benchmarks show that utilizing ITD-aware schemes for thermal management improves the performance of the processor in terms of speed and energy-delay-product by 8.55% and 4.4%, respectively.

Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have necessitated system level thermal management solutions for multi-core systems. Dynamic thermal management (DTM) techniques monitor on-chip temperature continuously and typically employs dynamic voltage and frequency scaling (DVFS) to lower the temperature when it exceeds a pre-defined threshold. State-of-the-art DTM solutions for multi-core systems include distributed DVFS (where each core can scale the voltage/frequency individually) and global DVFS (where all cores scale voltage/frequency simultaneously). Distributed DVFS generally offers higher performance than global DVFS, but it is hard to implement and has major scalability issues.

Due to technology advances and complexity of designs, thermal issue is a bottleneck in electronics designs. Various dynamic thermal management techniques have been proposed to address this issue. To effectively apply thermal management techniques, providing an accurate thermal map of chips is highly required. For this goal, a network of temperature sensors ought to be provided. There are various implementations for temperature sensors and network of sensors on Field Programmable Gate Arrays (FPGAs). This work defines and formulates four metrics and criteria, in terms of area, thermal, and power overheads and thermal map accuracy for exploring and evaluating efficiency of different implementations of Ring Oscillator-based Temperature Sensor (ROTS) networks on FPGAs and reports the comparison results for 12 networks with various sensor configurations. According to our metrics and experiments, the sensor that it is composed of NOT gates with open latches and RNS ring counter has lower thermal and power overheads compared to other configurations. Moreover, in this work, a new ROTS is presented that occupies 25% less resources than the most compact temperature sensor. Also, it provides 1.72 times higher sensitivity than the best sensitive ROTS design.

Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor

In aggressively scaled technologies, reliability concerns such as oxide breakdown have become a key issue. Dynamic reliability management (DRM) has been proposed as a mechanism to dynamically explore the trade-off between system performance and reliability margin. However, existing DRM methods are hampered by the fact that they do not accurately model spatial and temporal variations in process and temperature parameters which have a strong impact on chip reliability. In addition, they make the simplifying assumption that the future workloads are identical to the currently observed one. This makes them sensitive to sudden workload variations and outliers. In this paper, we present a novel workload-aware dynamic reliability management framework that accounts for local variations in both the process and temperature. The reliability estimation, along with the predicted remaining workload is fed to a dynamic voltage/frequency scaling module to manage the system reliability and optimize processor performance. Using a fast on-line analytical/table-look-up method we demonstrate an average error of 1% with up to 5 orders of magnitude speedup compared to Monte Carlo simulation. Experiments on an Alpha-like processor show our DRM framework fully utilizes the available margin and achieves 28.7% performance improvement on average.

Dynamic thermal management (DTM) techniques of three‐dimensional (3D) Network‐on‐Chips (NoCs) are employed to rescue the chip from thermal difficulties. Reactive routing algorithms, which utilise router throttling technique as a popular DTM, disregard distribution of heat generation of routers resulting in more throttled routers as well as long packet delays in throttled processing elements. This study proposes a reactive routing algorithm for 3D NoCs to (i) dynamically detour packets from hot zones containing throttled routers and (ii) minimise the number of required router throttling in the network. The proposed routing algorithm defines two virtual networks to enhance the path diversity for packets in each layer of 3D NoCs. The selection of diverse paths distributes heat generation to alleviate the thermal variance. The proposed routing algorithm is analysed by turn model to achieve deadlock freedom. Access Noxim simulator is also used to evaluate the performance and the thermal behaviour of the proposed routing algorithm in the variety of conditions. Results show that the proposed routing algorithm improves temperature variance by 9–39% and reduces number of throttled routers by 16–86%, which is achieved at the cost of one extra virtual channel per each physical channel in the XY ‐plane.

Reliability failure mechanisms, such as time-dependent dielectric breakdown (TDDB), electromigration, and negative bias temperature instability (NBTI), have become a key concern in integrated circuit (IC) design. The traditional approach to reliability qualification assumes that the system will operate at maximum performance continuously under worst case voltage and temperature conditions. In reality, due to widely varying environmental conditions and an increased use of dynamic control techniques, such as dynamic voltage scaling and sleep modes, the typical system spends a very small fraction of its operational time at maximum voltage and temperature. In this paper, we show how this results in a reliability ";slack"; that can be leveraged to provide increased performance during periods of peak processing demand. We develop a novel, real time reliability model based on workload driven conditions. Based on this model, we then propose a new dynamic reliability management (DRM) scheme that results in 20%-35 % performance improvement during periods of peak computational demand while ensuring the required reliability lifetime.

Graphics workloads are highly dynamic in nature, using multi-threaded SIMD execution units (EUs), fixed-function units, samplers, and media accelerators to provide ever-increasing amounts of graphics performance. These workloads are often limited by power and thermal constraints, requiring dynamic voltage/frequency scaling (DVFS) of the graphics processor (GPU). This coarse-grain DVFS, driven by a power-management IC (PMIC) setting a shared rail voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</inf> ), incurs performance loss while waiting for PLL re-lock and slow-rail voltage transitions. In addition, it does not allow a performance-critical unit (e.g. an EU) to use on demand a higher V/F (e.g. for EU turbo) without an energy penalty for the rest of the GPU.

As mobile devices of embedded systems prevail in our daily life, energy saving emerges as one very important issue and power management techniques are desirable. This paper presents the design and the implementation of a dynamic power management mechanism (DPMM) for embedded systems running micro-kernel operating systems. The DPMM is composed of policy manager, DVFS (Dynamic Voltage Frequency Scaling) controller, DPM (Dynamic Power Management) server, resource management flags, and DPM library. They are imple-mented to execute on an embedded system platform equipped with an XScale PXA270 processor and various I/O interfaces or devices running Zinix micro-kernel operating system. Testing results indicate that this DPMM effectively achieves power management in the system.

Small size of the sensor nodes put constraint on the hardware capabilities and battery supported on it. Though power optimization is a real challenge in all WSN applications, power saving at the cost of data loss is not at all preferable. Very small buffer sizes cannot store the increased data arrival at the time of event occurrences and data gets lost due to buffer overflow. Data loss within the node occurs before transmission mainly either data gets timed out or due to buffer overflows. Both of these situations can be handled using CAP management techniques at individual sensor nodes. Here Dynamic Voltage Frequency Scaling (DVFS) and Dynamic Modulation Scaling (DMS) techniques are used for optimization of power consumed by processor and transmitter respectively. We have considered that DVFS and DMS are coordinated together so that whenever processor changes its processing speed, transmitter also changes its transmission rate and minimum data loss occurs at the intermediate buffer. In this paper we have discussed adaptive threshold policy for selecting a particular state of sensor node and compared the results with fixed threshold policy. CAP management along with adaptive threshold policy improves the lifetime of sensor nodes and also reduces the data loss before transmission.

The amazing integration densities achieved by current submicron technologies pay the price of increasing static power dissipation with the corresponding rise in heat density. Dynamic thermal management (DTM) techniques provide thermal-efficient solutions to balance or equally distribute possible on-chip hot spots. Accurate sensing of on-chip temperature is required by optimally allocating smart temperature sensors in the silicon. In this paper, we introduce an ultra low-power (1.05 - 65.5 nW at 5 samples/s) tiny (10250 mum2) CMOS smart temperature sensor based on the thermal dependency of the leakage current. The proposed sensor outperforms all previous works, as far as area and power consumption are concerned (more than 85% reduction in both cases), while still meeting the accuracy constraints imposed by target application domains. Furthermore, a specific interface based on the use of a logarithmic counter has been implemented to digitalize the temperature sensing. These facts, in conjunction with the full compatibility of the sensor with standard CMOS processes, allow the easy integration of many of these tiny sensors in any VLSI layout, making them specially suitable for modern DTM implementations.

Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density. Extremely high power density, thus the very high on-chip temperature, not only significantly increases the packaging and cooling costs, but also creates tremendous difficulties in chip leakage control and reliability. Being a major contributor to chip transistor budget and die area, caches account for a significant share of the overall processor power consumption, including both dynamic and leakage power. This work analyzes the thermal behavior of subarrays within a conventional data cache when running a set of applications from the SPEC2000 benchmark suite, and proposes two new subarraying schemes, namely, the separated scheme and the interleaved scheme, to improve the thermal behavior of subarrays in terms of more predictable behavior and reduced subarray temperatures. These optimizations can be also combined with dynamic thermal management (DTM) techniques to further improve the efficiency of thermal management. The impact of leakage control on the subarray thermal behavior is also evaluated.

Recent mobile devices adopt high-performance processors to support various functions. As a side effect, higher performance inevitably leads to power density increase, eventually resulting in thermal problems. In order to alleviate the thermal problems, off-the-shelf mobile devices rely on dynamic voltage-frequency scaling (DVFS)-based dynamic thermal management (DTM) schemes. Unfortunately, in the DVFS-based DTM schemes, an excessive number of DTM operations worsen not only performance but also power efficiency. In this paper, we propose a temperature-aware DVFS scheme for Android-based mobile devices to optimize power or performance depending on the option. We evaluate our scheme in the off-the-shelf mobile device. Our evaluation results show that our scheme saves energy consumption by 12.7%, on average, when we use the power optimizing option. Our scheme also enhances the performance by 6.3%, on average, by using the performance optimizing scheme, still reducing the energy consumption by 6.7%.

In this paper, we propose a novel accuracy-reconfigurable stochastic computing (ARSC) framework for dynamic reliability and power management. Different than the existing stochastic computing works, where the accuracy versus power/energy trade-off is carried out in the design time, the new ARSC design can change accuracy or bit-width of the data in the run-time so that it can accommodate the long-term aging effects by slowing the system clock frequency at the cost of accuracy while maintaining the throughput of the computing. We validate the ARSC concept on a discrete cosine transformation (DCT) and inverse DCT designs for image compressing/decompressing applications, which are implemented on Xilinx Spartan-6 family XC6SLX45 platform. Experimental results show that the new design can easily mitigate the long-term aging induced effects by accuracy trade-off while maintaining the throughput of the whole computing process using simple frequency scaling. We further show that one-bit precision loss for the input data, which translated to 3.44dB of the accuracy loss in term of Peak Signal to Noise Ratio (PSNR) for images, we can sufficiently compensate the NBTI induced aging effects in 10 years while maintaining the pre-aging computing throughput of 7.19 frames per second. At the same time, we can save 74% power consumption by 10.67dB of accuracy loss. The proposed ARSC computing framework also allows much aggressive frequency scaling, which can lead to order of magnitude power savings compared to the traditional dynamic voltage and frequency scaling (DVFS) techniques.

Dynamic Thermal Management techniques have been widely accepted as a thermal solution for their low cost and simplicity. The techniques have been used to manage the heat dissipation and operating temperature to avoid thermal emergencies, but are not aware of application behavior in Chip Multiprocessors (CMPs). In this paper, we propose a temperature-aware scheduler based on applications' thermal behavior groups classified by a K-means clustering method in multicore systems. The application's thermal behavior group has similar thermal pattern as well as thermal parameters.With these thermal behavior groups, we provide thermal balances among cores with negligible performance overhead. We implement and evaluate our schemes in the 4-core (Intel Quad Core Q6600) and 8-core (two Quad Core Intel XEON E5310 processors) systems running several benchmarks. The experimental results show that the temperature-aware scheduler based on thermal behavior grouping reduces the peak temperature by up to 8degC and 5degC in our 4-core system and 8-core system with only 12% and 7.52% performance overhead, respectively, compared to L.inux standard scheduler.