Optimizing the thermal behavior of subarrayed data caches

Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have necessitated system level thermal management solutions for multi-core systems. Dynamic thermal management (DTM) techniques monitor on-chip temperature continuously and typically employs dynamic voltage and frequency scaling (DVFS) to lower the temperature when it exceeds a pre-defined threshold. State-of-the-art DTM solutions for multi-core systems include distributed DVFS (where each core can scale the voltage/frequency individually) and global DVFS (where all cores scale voltage/frequency simultaneously). Distributed DVFS generally offers higher performance than global DVFS, but it is hard to implement and has major scalability issues.

Temperature control of the new-generation integrated multicore system is challenging. This is because the leakage power, which is significant in modern systems, is nonlinearly related to temperature, resulting in a complex nonlinear control problem in thermal management. In this article, a new dynamic thermal management (DTM) method with compact piecewise linear (PWL) model based predictive control is proposed to solve the nonlinear control problem. First, a compact PWL thermal model, which takes dynamic power as input, is built by combining multiple local compact linear thermal models expanded at several Taylor expansion points. These local compact linear thermal models are obtained by sampling-based model order reduction with high accuracy. Their Taylor expansion points are selected by a systematic scheme, which exploits the thermal behavior property of the multicore chips. Based on the compact PWL thermal model, a new predictive control method is proposed to compute the future power recommendation for DTM. By approximating the nonlinearity accurately with the compact PWL thermal model and being equipped with predictive control technique, the new DTM achieves an overall high quality temperature management with smooth and accurate temperature tracking. Experimental results show that the new method outperforms the linear model predictive control based method and the echo state network based predictive thermal management method in temperature management quality with lower computing overhead.

The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues. However, the thermal problems become more exacerbated because of the larger power density and the heterogeneous thermal conductance in different silicon layer of 3D NoC. To regulate the system temperature, the Dynamic Thermal Management (DTM) techniques will be triggered when the device is thermal-emergent. However, these kinds of reactive DTM schemes result in significant system performance degradation. In this paper, we propose a proactive DTM with vertical throttling (PDTM-VT) scheme, which is controlled by the distributed Thermal Management Unit (TMU) of each NoC node. Based on the expected temperature resulted from the proposed thermal prediction model, the TMU can early control the temperature of the thermal-emergent device. The experimental results show that the proposed thermal prediction model has less than 0.25% prediction error against actual temperature measurement within 50ms. Besides, the PDTM-VT can reduce 11.84%~23.18% thermal-emergent nodes and improve 0.47%~47.90% network throughput.

Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor

With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management(DTM) as processors and hard drives did. The DTM of memories, nevertheless, is different in that it should take the processor performance and power consumption into consideration. Existing schemes have ignored that. In this study, we investigate a new approach that controls the memory thermal issues from the source generating memory activities - the processor. It will smooth the program execution when compared with shutting down memory abruptly, and therefore improve the overall system performance and power efficiency. For multicore systems, we propose two schemes called adaptive core gating and coordinated DVFS. The first scheme activates clock gating on selected processor cores and the second one scales down the frequency and voltage levels of processor cores when the memory is to be over-heated. They can successfully control the memory activities and handle thermal emergency. More importantly, they improve performance significantly under the given thermal envelope. Our simulation results show that adaptive coregating improves performance by up to 23.3% (16.3% on average) on a four-core system with FB-DIMM when compared with DRAM thermal shutdown; and coordinated DVFS with control-theoretic methods improves the performance by up to 18.5% (8.3% on average).

Dynamic thermal management (DTM) techniques of three‐dimensional (3D) Network‐on‐Chips (NoCs) are employed to rescue the chip from thermal difficulties. Reactive routing algorithms, which utilise router throttling technique as a popular DTM, disregard distribution of heat generation of routers resulting in more throttled routers as well as long packet delays in throttled processing elements. This study proposes a reactive routing algorithm for 3D NoCs to (i) dynamically detour packets from hot zones containing throttled routers and (ii) minimise the number of required router throttling in the network. The proposed routing algorithm defines two virtual networks to enhance the path diversity for packets in each layer of 3D NoCs. The selection of diverse paths distributes heat generation to alleviate the thermal variance. The proposed routing algorithm is analysed by turn model to achieve deadlock freedom. Access Noxim simulator is also used to evaluate the performance and the thermal behaviour of the proposed routing algorithm in the variety of conditions. Results show that the proposed routing algorithm improves temperature variance by 9–39% and reduces number of throttled routers by 16–86%, which is achieved at the cost of one extra virtual channel per each physical channel in the XY ‐plane.

The amazing integration densities achieved by current submicron technologies pay the price of increasing static power dissipation with the corresponding rise in heat density. Dynamic thermal management (DTM) techniques provide thermal-efficient solutions to balance or equally distribute possible on-chip hot spots. Accurate sensing of on-chip temperature is required by optimally allocating smart temperature sensors in the silicon. In this paper, we introduce an ultra low-power (1.05 - 65.5 nW at 5 samples/s) tiny (10250 mum2) CMOS smart temperature sensor based on the thermal dependency of the leakage current. The proposed sensor outperforms all previous works, as far as area and power consumption are concerned (more than 85% reduction in both cases), while still meeting the accuracy constraints imposed by target application domains. Furthermore, a specific interface based on the use of a logarithmic counter has been implemented to digitalize the temperature sensing. These facts, in conjunction with the full compatibility of the sensor with standard CMOS processes, allow the easy integration of many of these tiny sensors in any VLSI layout, making them specially suitable for modern DTM implementations.

Increasing on-chip temperature in SoC designs has reinforced the need for Dynamic Thermal Management (DTM). The conventional DTM techniques adopted in microprocessors based on DVFS are not suitable in the context of SoCs as they tend to have multiple voltage and frequency domains. In this paper we propose a reactive and a predictive DTM technique using bus arbitration. Based on the thermal profile the bus grants and hence the bus transactions are controlled. This regulates the data flow which reduces the activity in the functional units. The results show that the on-chip temperature can be maintained 3–5°C below the chip temperature threshold with a worst case performance penalty of 5% and a fast response time of at most 5 clock cycles. The hardware cost of implementing the proposed scheme is 3619.7μm2 in 45nm technology, which is less than 0.06% of the chip area. Apart from its simplicity, lower cost and effectiveness, the solution is non-intrusive on the design and scalable to many cores.

Power semiconductors and chips are essential in modern electronics, driving applications from personal devices and data centers to energy technologies, vehicles, and Internet infrastructure. However, efficient heat dissipation remains a critical challenge, directly affecting their performance, reliability, and lifespan. High-power electronics based on wide- and ultrawide-bandgap semiconductors can exhibit power densities exceeding 10 kW/cm2, hundreds of times higher than digital electronics, posing significant thermal management challenges. Addressing this issue requires advanced materials and interface engineering, alongside a comprehensive understanding of materials physics, chemistry, transport dynamics, and various electronic, thermal, and mechanical properties. Despite progress in thermal management solutions, the complex interplay of phonons, electrons, and their interactions with material lattices, defects, boundaries, and interfaces presents persistent challenges. This Account highlights key advancements in thermal management for power semiconductors and chips, with a focus on our group's recent contributions. Our approach addresses several critical issues: (1) developing materials with ultrahigh thermal conductivity for enhanced heat dissipation, (2) reducing thermal boundary resistance between power semiconductors and emerging 2D materials, (3) improving thermal and mechanical contacts between chips and heat sinks, (4) innovating dynamic thermal management solutions, and (5) exploring novel principles of thermal transport and design for future technologies. Our research philosophy integrates multiscale theoretical predictions with experimental validation to achieve a paradigm shift in thermal management. By leveraging first-principles calculations, the recent studies redefined traditional criteria for high-thermal-conductivity materials. Guided by these insights, we developed boron arsenide and boron phosphide, which exhibit record-high thermal conductivities of up to 1300 W/mK. Through phonon band structure engineering, we reduced TBR in GaN/BAs interfaces by over 8-fold compared to GaN/diamond interfaces. The combination of low TBR and high thermal conductivity significantly reduced hotspot temperatures, setting new benchmarks in thermal design for power electronics. We further explored the anisotropic TBR properties of two-dimensional materials and Moiré patterns in twisted graphene, expanding the thermal design landscape. To address challenges at device-heat sink interfaces, we developed self-assembled boron arsenide composites with a thermal conductivity of 21 W/mK and exceptional mechanical compliance (∼100 kPa). These composites provide promising solutions for thermal management in flexible electronics and soft robotics. In dynamic thermal management, we pioneered the concept of solid-state thermal transistors, enabling electrically controlled heat flow with unparalleled tunability, speed, reliability, and compatibility with integrated circuit fabrication. These innovations not only enhance thermal performance but also enable the exploration of novel transport physics, improving our fundamental understanding of thermal energy transport under extreme conditions. Looking forward, we reflect on remaining challenges and identify opportunities for further advancements. These include scaling up the production of high-performance materials, integrating thermal solutions with existing manufacturing processes, and uncovering new physics to inspire next-generation power electronics technologies. By addressing these challenges, we aim to inspire future codesign strategies that enable the development of more efficient, reliable, sustainable, and high-performance electronic systems.

Register files are responsible for the majority of thermal emergencies in high performance processors. In this paper, we propose compiler-microarchitecture cooperative techniques to reduce the performance penalty incurred by existing thermal management schemes. Our experiments show that an existing dynamic thermal management (DTM) scheme may result in 47% performance degradation at 45 nm technology node as compared to the ideal case where the processor can sustain any thermal emergency and no DTM is applied. We also evaluate performance degradation of a couple of other DTMs and demonstrate that our cooperative policy can bring down this performance penalty. Our approach shows the consistent effectiveness even with the technology scaling.

With ever-increasing power densities, Dynamic Thermal Management (DTM) techniques have become mainstream in today's systems. An important component of such techniques is the thermal trigger. It has been shown that predictive thermal triggers can outperform reactive ones. In this paper, we present a novel trade-off space of predictive thermal triggers, and compare different approaches proposed in the literature. We argue that run-time adaptability is a crucial parameter of interest. We present a run-time adaptable thermal simulator compatible with arbitrary sensor configuration based on the Neural Network (NN) simulator presented in. We present experimental results on Niagara UltraSPARC T1 chip with real-life benchmark applications. Our results quantitatively establish the effectiveness of the proposed simulator for reducing (by up to 90%), the otherwise unacceptably high errors, that can arise due to expected leakage current variation and design-time thermal modeling errors.

This paper presents a thermal sensing and VLSI thermal management scheme using an array of on-chip all-digital delay-line based temperature sensors. A fully digital self-calibration method that removes the temperature sensors' sensitivities to supply voltage and process variations is proposed. The proposed calibration method assigns a unique correction factor, N C to each sensor, making all the sensors' calibrated outputs to be the same at start-up. The correction factor is updated when supply voltage variations are detected. Only one calibration block is required to calibrate multiple delay-line based temperature sensors sequentially. For each additional sensor, only additional registers for storing N C are required. The proposed self-calibrated temperature sensors are demonstrated on an Altera Cyclone IV FPGA based VLSI thermal management system. Runtime thermal profiles for four cores mapped on the Cyclone IV FPGA chip using a hybrid dynamic thermal management (DTM) method are obtained. The percentage of time that each core spent in a particular temperature range is plotted in a histogram. A comparison of different DTM techniques demonstrates that the proposed hybrid DTM reduces the amount of time that the MPSoC spent at higher temperatures and larger thermal gradients, by 10% and 21%, respectively. In addition, the proposed hybrid DTM offers a 10% improvement in the average processing rate (instructions per second) when compared with the conventional global DFS approach.

As the demand for reliable power systems comprised of parallel-connected converter units continue to increase the need for optimized load sharing techniques rises accordingly. This fact is emphasized by a power system minimization trend that tends to shrink the available PCB area set aside for the power system. These contradictive trends feed the research in topics such as advanced thermal management and dynamic thermal management. Implementation of the latter topic usually requires the use of complicated controllers that continuously monitors the thermal working environment and key components within the system. If the thermal stress exceeds preset limits the controller react according to a predetermined sequence to minimize the damaging effects of excessive thermal stress. This paper combines the dynamic thermal management with the load sharing. It is hereby effectively ensured that the parts count is kept to a minimum while providing a dynamic optimization of parameters such as average and absolute system temperatures as well as overall system reliability. The latter aspect is achieved by redistributing the current throughput of each converter, which in turn results in equal thermal conditions as opposed to well-known and widely used current sharing technique's intent to establish equal currents.

Due to technology advances and complexity of designs, thermal issue is a bottleneck in electronics designs. Various dynamic thermal management techniques have been proposed to address this issue. To effectively apply thermal management techniques, providing an accurate thermal map of chips is highly required. For this goal, a network of temperature sensors ought to be provided. There are various implementations for temperature sensors and network of sensors on Field Programmable Gate Arrays (FPGAs). This work defines and formulates four metrics and criteria, in terms of area, thermal, and power overheads and thermal map accuracy for exploring and evaluating efficiency of different implementations of Ring Oscillator-based Temperature Sensor (ROTS) networks on FPGAs and reports the comparison results for 12 networks with various sensor configurations. According to our metrics and experiments, the sensor that it is composed of NOT gates with open latches and RNS ring counter has lower thermal and power overheads compared to other configurations. Moreover, in this work, a new ROTS is presented that occupies 25% less resources than the most compact temperature sensor. Also, it provides 1.72 times higher sensitivity than the best sensitive ROTS design.

Dynamic Thermal Management (DTM) emerged as a solution to address the reliability challenges with thermal hotspots and unbalanced temperatures. DTM efficiency is highly affected by the accuracy of the temperature information presented to the DTM manager. This work aims to investigate the effect of inaccuracy caused by the deep sub-micron (DSM) noise during the transmission of temperature information to the manager on DTM efficiency. A simulation framework has been developed and results show up to 38% DTM performance degradation and 18% unattended cycles in emergency temperature under DSM noise. The finding highlights the importance of further research in providing reliable on-chip data transmission in DTM application.