Compact Piecewise Linear Model Based Temperature Control of Multicore Systems Considering Leakage Power

The paper presents a compact thermal model of an electronic component enclosed in a D2Pak case.The model includes convection cooling and is compared to a linear model with isothermal boundary condition.The model presented is a static model.

The goal of this research is to develop a Dynamic Compact Thermal Model (DCTM) of electronic packages. The general objectives of thermal modeling are to increase the accuracy of electrical analysis by taking the effect of temperature variation into consideration, predicting the reliability of the product, and acquiring the information which is necessary to design the cooling system in order to enhance the performance of the electronic systems. The project is focused on generating the dynamic compact thermal model of electronic packages so that the transient thermal behaviors of the package could be predicted fast and accurately. The approach proposed by DELPHI consortium (a collaborative European project) for static compact thermal model generation is extended in this work to generate the dynamic compact model of a BGA package represented by a RC network or admittance matrix. Two steps performed as the methodology of dynamic compact model generation in this work are: 1- A static compact thermal model of BGA package is generated and validated from the static thermal simulation and 2- A RC network is proposed as the contribution of this work and calculated by optimization as the dynamic compact thermal model of the package using the data of transient simualtion. The size of the proposed RC network then is optimized by eliminating some capacitors from the original RC network and validated by comparing its output to the ouptut of finite element simulation. COMSOL©, a Finite element analysis tool is used for thermal simulation and detailed steady state and transient model generation. The optimization algorithm implemented for both static and dynamic compact model generation is Nelder-Mead multidimensional optimization which is realized by MATLAB© programming. The obtained results from the compact models for both static and dynamic analysis of the BGA package are in agreement with the detailed thermal model results and with the available results in literature.

Compact thermal models have been constructed for different levels in electronic systems with a variable degree of success. Many of these models suffer from the need to make ad-hoc assumptions about the number of nodes to be used in the model and require a predefined set of boundary conditions that are used to generate the compact model. In this work first steps towards a method that is firmly based on physical understanding and mathematical rigor are presented for linear compact models. The method gives general constraints on the form of compact models that will ensure an adequate description of thermal systems. Furthermore, the method allows reduction of the generating set of boundary conditions to an absolute minimum while at the same time providing information about the errors that are inevitable in the predictions of a compact model. Using these error estimates it is possible to determine the optimal number of nodes to be used in the compact model for a desired accuracy. The method will be applied to the benchmark defined for this purpose.

In this article, we propose a new behavioral thermal modeling method for fast building performance analysis, which is critical for energy-efficient smart building control and management. The new approach is based on two recurrent neutral network architecture to obtain the compact nonlinear thermal models for complicated building. We start with a more realistic building simulation program, EnergyPlus, from Department of Energy, to model some practical buildings such as office buildings and data centers. EnergyPlus can model the various time-series inputs to a building such as ambient temperature, heating, ventilation, and air-conditioning (HVAC) inputs, power consumption of electronic equipment, lighting and number of occupants in a room sampled in each hour and produce resulting temperature traces of zones (rooms). In this work, we apply two recurrent neural network (RNN) architectures to build the non-linear compact thermal model of the building: one is non-linear state-space RNN architecture (NLSS), which has global feedbacks, and the other one is Elman's RNN architecture (ELNN), which has local feedbacks in each layer. We give a simple formula to calculate the RNN layer number, layer size to configure RNN architecture to avoid overfitting and underfitting problems. A cross-validation based training technique is further applied to improve predictable accuracy of models. Experimental results from a case study of three buildings show that ELNN and NLSS can both build very accurate building thermal models for the 2-zone and 5-zone building cases: both of them have average errors from around 1% to 1.5% for the two buildings. For the more complex 6-zone building case, ELNN outperforms NLSS with maximum errors 16% against 23%. But both methods have 2.2% average errors.

Dose-response meta-analysis (DRMA) is widely employed in establishing the potential dose-response relationship between continuous exposures and disease outcomes. However, there is no valid DRMA method readily for discrete exposures, especially when the possible dose-response trend not likely to be linear. We proposed a piecewise linear DRMA model as a solution to this issue. We illustrated the methodology of piecewise linear model in both one-stage DRMA approach and two-stage DRMA approach. The method by testing the equality of slopes of each piecewise was employed to judge if there is "piecewise effect" against a simple linear trend. We then used sleep (continuous exposure) and parity (discrete exposure) data as examples to illustrate how to apply the model in DRMA using the Stata code attached. We also empirically compared the slopes of piecewise linear model with simple linear as well as restricted cubic spline model. Both one-stage and two-stage piecewise linear DRMA model fitted well in our examples, and the results were similar. Obvious "piecewise effects" were detected in both the two samples by the method we used. In our example, the new model showed a better fitting effect and practical, reliable results compared to the simple linear model, while similar results for to restricted cubic spline model. Piecewise linear function is a valid and straightforward method for DRMA and can be used for discrete exposures, especially when the simple linear function is under fitted. It represents a superior model to linear model in DRMA and may be an alternative model to the nonlinear model.

Due to the superlinear dependence of leakage power consumption on temperature, and spatial variations in on-chip thermal profiles, methods of leakage power estimation that are known to be accurate require detailed knowledge of thermal profiles. Leakage power depends on the integrated circuit (IC) thermal profile and circuit design style. Here, we show that piecewise linear models can be used to permit accurate leakage estimation over the operating temperature ranges of the ICs. We then show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have a similar impact on the average temperature of the layer. These two observations support the proof that, for wide ranges of design styles and operating temperatures, extremely fast, coarse-grained thermal models, combined with piecewise linear leakage power consumption models, enable the estimation of chip-wide leakage power consumption. These results are further confirmed through comparisons with leakage estimates based on detailed, time-consuming thermal analysis techniques. Experimental results indicate that, when compared with a leakage analysis technique that relies on accurate spatial temperature estimation, the proposed technique yields a 59,259× to 1,790,000× speedup in estimating leakage power consumption, while maintaining accuracy.

The construction and usage of compact thermal models (CTMs), for the thermal analysis as well as the design of cooling devices for electronic systems, are reviewed. These models have many advantages over the so called detailed models based on 3D simulations, mainly being a convenient and simple quantitative description of the modeled object, when constructional details are either unavailable or too detailed to be of use at the desired level of analysis. However, CTMs have manifested some deficiencies in many cases, in particular, multiple chip modules (MCM) and stacked dies. The opposite approach, detailed modeling, is more reliable, although extremely heavy. A new approach is proposed that solves this dilemma by bridging the gap between compact and detailed models. While retaining all advantages of CTMs, i.e., having a limited number of degrees of freedom and not requiring detailed constructional features, it can attain any required precision level depending on the degree of complexity adopted. It gives reliable results covering all operating conditions including MCM and stacked dies. Moreover, it gives access to data on surface temperature gradients that were never obtained before by compact models and are highly important for reliability issues.

This paper presents a comparative study of two widely accepted model predictive control schemes based on mixed logical dynamical (MLD) and nonlinear modeling approaches with application to a continuous stirred tank reactor (CSTR) system. Specifically, we approximate the nonlinear behavior of a CSTR system with multiple local linear models in a MLD framework. The main benefit of such a scheme is the significant improvement in model accuracy when compared with a single linearized model. The benefits and trade-offs associated with predictive control laws synthesized using MLD and nonlinear modeling approaches are also compared.

This paper presents a thermal sensing and VLSI thermal management scheme using an array of on-chip all-digital delay-line based temperature sensors. A fully digital self-calibration method that removes the temperature sensors' sensitivities to supply voltage and process variations is proposed. The proposed calibration method assigns a unique correction factor, N C to each sensor, making all the sensors' calibrated outputs to be the same at start-up. The correction factor is updated when supply voltage variations are detected. Only one calibration block is required to calibrate multiple delay-line based temperature sensors sequentially. For each additional sensor, only additional registers for storing N C are required. The proposed self-calibrated temperature sensors are demonstrated on an Altera Cyclone IV FPGA based VLSI thermal management system. Runtime thermal profiles for four cores mapped on the Cyclone IV FPGA chip using a hybrid dynamic thermal management (DTM) method are obtained. The percentage of time that each core spent in a particular temperature range is plotted in a histogram. A comparison of different DTM techniques demonstrates that the proposed hybrid DTM reduces the amount of time that the MPSoC spent at higher temperatures and larger thermal gradients, by 10% and 21%, respectively. In addition, the proposed hybrid DTM offers a 10% improvement in the average processing rate (instructions per second) when compared with the conventional global DFS approach.

The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues. However, the thermal problems become more exacerbated because of the larger power density and the heterogeneous thermal conductance in different silicon layer of 3D NoC. To regulate the system temperature, the Dynamic Thermal Management (DTM) techniques will be triggered when the device is thermal-emergent. However, these kinds of reactive DTM schemes result in significant system performance degradation. In this paper, we propose a proactive DTM with vertical throttling (PDTM-VT) scheme, which is controlled by the distributed Thermal Management Unit (TMU) of each NoC node. Based on the expected temperature resulted from the proposed thermal prediction model, the TMU can early control the temperature of the thermal-emergent device. The experimental results show that the proposed thermal prediction model has less than 0.25% prediction error against actual temperature measurement within 50ms. Besides, the PDTM-VT can reduce 11.84%~23.18% thermal-emergent nodes and improve 0.47%~47.90% network throughput.

In this paper it is shown how parametric dynamic compact thermal models can be exploited for the calibration of detailed thermal models of electronic components and packages. A constrained least square fit of the thermal response of a parametric dynamic compact thermal model, having as parameters the material thermal properties and geometrical details to be calibrated, onto the measured temperature response is performed. Numerical results show that the use of parametric dynamic compact thermal models instead of detailed compact thermal models, in conjunction with an optimization algorithm solving the constrained least square problem, can reduce the computational time for calibration by more than two orders of magnitude.

Large progress has been realized in modeling conduction heat transfer problems over the past decade by the introduction of high performance compact thermal models (CTMs) mainly developed for thermal design of complicated electronic systems. The objective of this paper is to generalize these advances to convective heat transfer. A new convective CTM is proposed, which offers many advantages over the traditional approach using the heat transfer coefficient (HTC). The latter is simply a zeroth order CTM. The HTC is quite handy and simple, but with unpredictable errors. It can be suitable for hand calculations of simple systems giving rather crude estimates. For a higher precision, users have no other option than time consuming 3D simulations. For large systems, in terms of number of components, 3D simulations can be rapidly impractical. The CTM bridges the gap between both approaches going gradually from “HTC” levels (low precision and calculations time) at the zeroth order, to 3D simulation precision and computing time levels at large orders. Fortunately, like for conduction, a CTM of order of few tens quickly approaches 3D simulation precision levels, while keeping computation time significantly lower than 3D simulation. Moreover, the CTM approach solves conjugate heat transfer problems in a quite elegant way. A “black box” model, developed for fluid domain alone, can be easily combined with classical CTM conduction models to generate good precision predictions for any combination of fluid/solid domains.

Register files are responsible for the majority of thermal emergencies in high performance processors. In this paper, we propose compiler-microarchitecture cooperative techniques to reduce the performance penalty incurred by existing thermal management schemes. Our experiments show that an existing dynamic thermal management (DTM) scheme may result in 47% performance degradation at 45 nm technology node as compared to the ideal case where the processor can sustain any thermal emergency and no DTM is applied. We also evaluate performance degradation of a couple of other DTMs and demonstrate that our cooperative policy can bring down this performance penalty. Our approach shows the consistent effectiveness even with the technology scaling.

Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density. Extremely high power density, thus the very high on-chip temperature, not only significantly increases the packaging and cooling costs, but also creates tremendous difficulties in chip leakage control and reliability. Being a major contributor to chip transistor budget and die area, caches account for a significant share of the overall processor power consumption, including both dynamic and leakage power. This work analyzes the thermal behavior of subarrays within a conventional data cache when running a set of applications from the SPEC2000 benchmark suite, and proposes two new subarraying schemes, namely, the separated scheme and the interleaved scheme, to improve the thermal behavior of subarrays in terms of more predictable behavior and reduced subarray temperatures. These optimizations can be also combined with dynamic thermal management (DTM) techniques to further improve the efficiency of thermal management. The impact of leakage control on the subarray thermal behavior is also evaluated.

Compact thermal models (CTMs) are simplified multi-nodal thermal resistor network representations of the detailed material and geometric structure of the electronic package. CTMs predict the thermal response of the package, in various environments, to within an accuracy of 2%. The junction temperature of the package is typically obtained by solving the linear algebraic network equations of the CTM, with the heat transfer to the ambience modeled by a convection coefficient obtained from handbooks, assuming identical ambient conditions imposed on all nodal surfaces. This approach may give misleading results as the ambience at each nodal surface can differ depending on the cooling flow patterns at that surface. In this work, a methodology is presented where the network equations of the CTM are integrated into the governing fluid flow and energy equations solved by computational fluid dynamics (CFD). The CTM+CFD approach predicts a significantly (20–30%) higher junction temperature as compared to the conventional CTM network solver method, even when the convection coefficient used in the latter case is obtained more accurately from CFD, rather than from handbook correlations. It is also found that CFD computations assuming uniform flux at the package surfaces (and ignoring the internal resistance of the package) vastly under-predict the junction temperature. The new approach offers a promising alternative for electronic package thermal design and is highly advantageous where the internal geometric and material configurations are not known due to proprietary concerns.