Lock bypassing

Electronic circuits: by E. J. Angelo, Jr. 450 pages, diagrams, 6 × 9 in. New York, McGraw-Hill Book Co. Inc., 1958.Price, $9.00.

Sorting strings and constructing digital search trees in parallel

As multiple processor systems become more widely accepted the importance of parallel programming increases. In this paper, approaches to the design and analysis of parallel algorithms are investigated. Through several examples, the importance of interprocessor communication in parallel processing is demonstrated. Various techniques that are applicable in the design and analysis of parallel algorithms are examined with emphasis on those techniques that incorporate communication aspects. The paper discusses several models of synchronous and asynchronous parallel computation and their use in analyzing algorithms. Relatively primitive methodologies for designing parallel algorithms are discussed and the need for more general and practical methodologies is indicated.

SummaryIn this chapter we will survey the techniques of the design of algorithms that effectively solve the computational problems of the previous chapters on parallel computers, reaching a substantial (and frequently dramatic) acceleration of the known sequential algorithms. In some cases this requires us to revise the sequential case approach or even to change it completely. We systematically review the state of the art in this area, in particular, the computational complexity estimates, the algorithms supporting them, and the major techniques for the design of effective parallel algorithms. We include several recent research results and techniques, particularly in sections 4 and 6 and in the appendices. The results of Appendices B and C on computing a maximal independent subset of a vector set and the techniques of the design of parallel algorithms demonstrated in Appendix A may be of interest for the designers of combinatorial and graph algorithms.

The sine cosine algorithm’s main idea is the sine and cosine-based vacillation outwards or towards the best solution. The first main contribution of this paper proposes an enhanced version of the SCA algorithm called as ESCA algorithm. The supremacy of the proposed algorithm over a set of state-of-the-art algorithms in terms of solution accuracy and convergence speed will be demonstrated by experimental tests. When these algorithms are transferred to the business sector, they must meet time requirements dependent on the industrial process. If these temporal requirements are not met, an efficient solution is to speed them up by designing parallel algorithms. The second major contribution of this work is the design of several parallel algorithms for efficiently exploiting current multicore processor architectures. First, one-level synchronous and asynchronous parallel ESCA algorithms are designed. They have two favors; retain the proposed algorithm’s behavior and provide excellent parallel performance by combining coarse-grained parallelism with fine-grained parallelism. Moreover, the parallel scalability of the proposed algorithms is further improved by employing a two-level parallel strategy. Indeed, the experimental results suggest that the one-level parallel ESCA algorithms reduce the computing time, on average, by 87.4% and 90.8%, respectively, using 12 physical processing cores. The two-level parallel algorithms provide extra reductions of the computing time by 91.4%, 93.1%, and 94.5% with 16, 20, and 24 processing cores, including physical and logical cores. Comparison analysis is carried out on 30 unconstrained benchmark functions and three challenging engineering design problems. The experimental outcomes show that the proposed ESCA algorithm behaves outstandingly well in terms of exploration and exploitation behaviors, local optima avoidance, and convergence speed toward the optimum. The overall performance of the proposed algorithm is statistically validated using three non-parametric statistical tests, namely Friedman, Friedman aligned, and Quade tests.


 
 
 
 Apriori algorithm is a classical algorithm of association rule mining and widely used for generating frequent item sets. However, the original Apriori algorithm has some limitation such as it needs to scan the dataset many times to discover all frequent itemset and generate huge number of candidate itemset. To overcome these limitations, researchers have made a lot of improvements to the Apriori such as candidate generation, without candidate generation, transaction reduction, partitioning, and sampling. When it comes to mine massive data, these algorithms failed to prove efficiency because limitation of the processing capacity, storage capacity, and main memory constraints. Therefore, parallel and distributed algorithms are developed to perform large-scale computing in ARM on multiple processors. However, the problems with most of the parallel and distributed framework are overheads of managing distributed system, lack of high level parallel programming language, and node failures. Hadoop-MapReduce is an efficient, scalable, and simplified programming model for massive data processing and it also available on cloud environment. Cloud computing offers huge computing resources, and capacities to solve big data challenges. Recently many parallel algorithms have been proposed on Hadoop-MapReduce to enhance the performance of Apriori algorithm but there are some drawbacks: since multiple scan over the dataset is needed to generate candidate itemset, it consume more execution time. The aim of this study is to propose a parallel Transaction Reduction MapReduce Apriori algorithm (TRMR-Apriori) which is reduce unnecessary transaction values and transactions from the dataset in parallel manner to overcome above problems. The experiments show that TRMR-Apriori is able to achieve better execution time to discover frequent itemset those of previous sequential ARM algorithms such as Apriori, AprioriTid, Eclat, and FP-Growth and the previous parallel algorithms such as PApriori, MRApriori, and Modified Apriori with different condition on homogeneous computing environment using Hadoop-MapReduce platform in cloud. Overall, the TRMR-Apriori shows the strength to extract the frequent itemset from massive dataset in cloud.
 
 
 
 

The authors provide optimal parallel solutions to several fundamental link distance problems set in trapezoided rectilinear polygons. All parallel algorithms are deterministic, run in logarithmic time, have an optimal time-processor product and are designed to run on EREW PRAM. The authors develop techniques (e.g. rectilinear window partition) for solving link distance problems in parallel which are expected to find applications in the design of other parallel computational geometry algorithms. They employ these parallel techniques for example to compute the link diameter, link center, and central diagonal of a rectilinear polygon. Their results also imply an optimal linear-time sequential algorithm for constructing a data structure to support rectilinear link distance queries between points.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Random sampling is an important tool in the design of parallel algorithms. Using random sampling it is possible to obtain simple parallel algorithms which are efficient in practice. We will focus on the use of random sampling in fundamental problems such as sorting, selection, list ranking and graph connectivity.

Designing irregular parallel algorithms with mutual exclusion and lock-free protocols

This paper examines the use of binary trees in the design of efficient parallel algorithms. Using binary trees, we develop efficient algorithms for several scheduling problems. The shared memory model for parallel computation is used. Our success in using binary trees for parallel computations, indicates that the binary tree is an important and useful design tool for parallel algorithms.

We review some of the results obtained in the last decade on the design and analysis of parallel factorization algorithms for solving dense linear systems of equations. After defining a model of computation, we introduce a graph-theoretic approach which allows to separate the design of a parallel algorithm into two independent parts construction of a task system, determination of the precedence constraints and of the task graph associated to a sequential algorithm construction of scheduling algorithms compatible with the task graph.

I'd like to propose a challenge to language designers interested in concurrency: how well do your favorite constructs support highly-concurrent data structures? For example, consider a real-time system consisting of a pool of sensor and actuator processes that communicate via a priority queue in shared memory. Processes execute asynchronously. When a sensor process detects a condition requiring a response, it records the condition, assigns it a priority, and places the record in the queue. Whenever an actuator process becomes idle, it dequeues the highest priority item from the queue and takes appropriate action. The conventional way to prevent concurrent queue operations from interfering is to execute each operation as a critical section: only one process at a time is allowed to access the data structure. As long as one process is executing an operation, any other needing to access the queue must wait. Although this approach is widely used, it has significant drawbacks.It is not fault-tolerant. If one process unexpectedly halts in the middle of an operation, then other processes attempting to access the queue will wait forever. Although it may sometimes be possible to detect the failure and preempt the queue, such detection takes time, it may be unreliable, and it may be impossible to restore the data structure to a consistent state.Critical sections force faster processes to wait for slower processes. Such waiting may be particularly undesirable in heterogeneous architectures, where some processors may be much faster than others. For example, a fast actuator process should not have to remain idle whenever a much slower sensor process is enqueuing a new item. Such waiting is also undesirable if each processor is dedicated to a single process, where delaying a process means idling a valuable hardware resource.Similar concerns arise even in systems not subject to real-time demands or failures. For example, process execution speeds may vary considerably if processors are multiplexed among multiple processes. If a process executing in a critical region takes a page fault, exhausts its quantum, or is swapped out, then other runnable processes needing to use that resource will be unable to make progress.An implementation of a concurrent object is wait-free if it guarantees that any process will complete any operation within a fixed number of steps, independent of the level of contention and the execution speeds of the other processes. To construct a wait-free implementation of the shared priority queue, we must break each enqueue or dequeue operation into a non-atomic sequence of atomic steps, where each atomic step is a primitive operation directly supported by the hardware, such as read, write, or fetch-and-add. To show that such an implementation is correct. It is necessary to show that (1) each operation's sequence of primitive steps has the desired effect (e.g., enqueuing or dequeuing an item) regardless of how it is interleaved with other concurrent operations, and (2) that each operation terminates within a fixed number of steps regardless of variations in speed (including arbitrary delay) of other processes.Support for wait-free synchronization requires genuinely new language constructs, not just variations on conventional approaches such as semaphores, monitors, tasks, or message-passing. I don't know what these constructs look like, but in this position paper, I would like to suggest some research directions that could lead, directly or indirectly, to progress in this area. We need to keep up with work in algorithms. To pick just one example, we now know that certain kinds of wait-free synchronization, e.g., implementing a FIFO queue from read/write registers, require randomized protocols in which processes flip coins to choose their next steps [3, 1]. The implications of such results for language design remain unclear, but suggestive. We also need to pay more attention to specification. Although transaction serializability has become widely accepted as the basic correctness condition for databases and certain distributed systems, identifying analogous properties for concurrent objects remains an active area of research [2].

In this book chapter, the authors discuss some important communication issues to obtain a highly scalable computing system. They consider the CGM (Coarse-Grained Multicomputer) model, a realistic computing model to obtain scalable parallel algorithms. The communication cost is modeled by the number of communication rounds and the objective is to design algorithms that require the minimum number of communication rounds. They discuss some important issues and make considerations of practical importance, based on our previous experience in the design and implementation of parallel algorithms. The first issue is the amount of data transmitted in a communication round. For a practical implementation to be successful they should attempt to minimize this amount, even when it is already within the limit allowed by the CGM model. The second issue concerns the trade-off between the number of communication rounds which the CGM attempts to minimize and the overall communication time taken in the communication rounds. Sometimes a larger number of communication rounds may actually reduce the total amount of data transmitted in the communications rounds. These two issues have guided us to present efficient parallel algorithms for the string similarity problem, used as an illustration.

Finite state automata are of fundamental importance in theory as well as applications in computer science. This dissertation presents several parallel algorithms for processing of them, including minimizing the number of states for a given finite state automaton, finding homing sequences for a given finite state automaton, converting a regular expression into an $\\varepsilon$-free nondeterministic finite automaton. Implementation of some algorithms, as well as their experimental results, are also given. For minimization of deterministic finite automata, we present a parallel algorithm and discuss its implementation on a practical parallel machine using data parallel and message passing paradigms. Its time complexity on a p processor EREW PRAM $(p\\le n)$ for inputs of size n is $O({n\\log\\sp2n\\over p}+\\log n\\ \\log p)$ uniformly on almost all instances. The work done by our algorithm is thus within a factor of $O(\\log n)$ of the best known sequential algorithm. The space used by our algorithm is linear in the input size. The actual resource requirements of our implementations are consistent with these estimates. For finding homing sequences of deterministic finite automata, we present both deterministic and randomized algorithms. Two randomized algorithms of time complexity $O(log\\sp2n)$ are given. One of the randomized algorithms produces a homing sequence of length $O(n\\ log\\sp2n)$ for almost all DFA's with n states. The deterministic algorithm is based on a well known sequential algorithm. The implementation of the deterministic parallel algorithm shows that it can handle randomly generated instances with millions of states, and all DFA's with thousands of states using currently available parallel machines. Finally, we present an efficient parallel algorithm for converting a regular expression into an $\\varepsilon$-free nondeterministic finite automaton. The resulting automaton is natural representation of a regular expression and has some important and practical uses in the document processing area. The time complexity of the algorithm is $O(\\log n)$ and the number of processors used is $O(n\\sp2).$

Offset computation for expanding a polyhedral object by an offset radius is a fundamental geometric process frequently used in manufacturing applications. This process combined with the triple-dexel representation solid model has become popular because of its robustness and compatibility with parallel processing using a graphics processing unit (GPU). In parallel geometric processing, conflicts between threads must be avoided. Thus, we propose a novel parallel offsetting algorithm free from conflicts between threads. The triple-dexel model is a combination of x-, y-, and z-axis-aligned dexel models. Each dexel model is defined based on an orthogonal grid given on a coordinate plane. We subdivide the grid into several sub-grids of a fixed size in advance. For each sub-grid, a block of GPU threads is assigned. As each GPU thread always processes different dexel elements from the other threads in this method, no conflict occurs. Our research group has previously presented a parallel offset computation algorithm for a polyhedral solid model that also uses a triple-dexel representation model and a GPU. In the previous algorithm, the surface polygons of the model are classified into several groups in advance. The parallel offset computation of multiple polygon groups is realized by selecting groups of polygon in which the offset processing of the polygons does not affect one another. This selection process is time-consuming. Computational experiments were performed to analyze the performance difference between the current algorithm and our previous algorithm. In our experiments, the current algorithm achieved speedups of 1.4 times to 3.2 times compared to our previous offsetting algorithm.