Logic Device Based on Skyrmion Annihilation

A half-adder (HA) and a full-adder (FA), using single-electron metal–oxide–semiconductor field-effect transistors (SE-MOSFET) hybrid circuits, are proposed. The proposed HA consists of three single-electron transistors (SETs), two enhancement-mode NMOSFETs and two depletion-mode NMOSFETs, and the proposed FA consists of four SETs, four enhancement-mode NMOSFETs, one enhancement-mode PMOSFET and three depletion-mode NMOSFETs. The total number of devices in the HA and the FA are 7 and 12, respectively. Compared with the conventional CMOS mirror FA with the 90 nm technology, the proposed FA can be constructed with 0.43 of devices and can operate with 5.6 of worst-case delay, 1/10.3 of average power consumption and 0.55 of power-delay product. The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are suitably determined. The basic operations of the proposed HA, HS, FA and FS have been successfully confirmed through SPICE circuit simulation based on the physical device model of the SET.

Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic synthesisers, which play a fundamental role in design today, play a minor role on most arithmetic circuits, performing some local optimisations but hardly improving the overall structure of arithmetic components. Architectural optimisations have been often studied manually, and only in the case of very common building blocks such as fast adders and multi-input adders, ad-hoc techniques have been developed. A notable case is multi-input addition, which is the core of many circuits such as multipliers, etc. The most common technique to implement multi-input addition is using compressor trees, which are often composed of carry-save adders (based on (3 : 2) counters, i.e., full adders). A large body of literature exists to implement compressor trees using large counters. However, all the large counters were built by using full and half adders recursively. In this paper we give some definite answers to issues related to the use of large counters. We present a general technique to implement large counters whose performance is much better than the ones composed of full and half adders. Also we show that it is not always useful to use larger optimised counters and sometimes a combination of various size counters gives the best performance. Our results show 15% improvement in the critical path delay. In some cases even hardware area is reduced by using our counters.

This paper presents an efficient carry save adder design with multiplexer based adder architecture, instead of using ripple carry adder it replaces this ripple carry adder with modified adder to achieve effective output. Using this modified adder it can obtain reduced gate delay with low power consumption. The proposed design is from 8bit to 64 bit carry save adder. Where 64bit designs are most widely used in digital systems in present technology. As ripple carry adder is one of the most common type adder used in various designs, it has a long propagation delay and also consume more area and power. To reduce the gate delay and power the carry save adder is customized as i.e. carry save adder is cascaded with the ripple carry adder. In ripple carry adder first block is a half adder followed by the full adder chain and ends with a half adder. These full adders in first and second stage are replaced with modified full adder.

This paper presents design of quaternary half adder and full adder based on multi valued logic.Adders are one of the important part of the processing element and hence it has a focus of research.Therefore implementation of adders using multi valued logic can prove to be very useful.The proposed half adder and full adders are designed with the help of transmission gate. These half adder and full adder are verified by simulation and appear to have very low power dissipation.

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

Nested skyrmion bags, as magnetic solitons with arbitrary integer topological charges (Q), hold potential for applications in data encoding. A crucial issue is the local manipulation of skyrmions within nested skyrmion bags to control the total Q. In this study, we explore different possible ground states and resonant excitation spectra of nested skyrmion bags through micromagnetic simulations. More importantly, we demonstrate that the manipulation of the Q of nested skyrmion bags can be achieved by using microwave magnetic fields, i.e., the inner, middle, and outer skyrmions within the nested skyrmion bags are selectively excited by using the diverse out-of-plane excitation modes. By calculating the energy of skyrmions, we further analyze the relationship between the annihilation of skyrmions at different positions and the out-of-plane microwave magnetic fields. Our findings present a promising approach for manipulating the Q of nested skyrmion bags, potentially advancing their application in storage and logic devices.

Recent researches are mostly focused on technology scaling as well as device size minimization design techniques following Moore’s law. Conventional computing architectures are unable to fulfill modern application demands. Memristor is a promising alternative device which has been developed by many researchers [2] to draw attention of its structure for numerous applications which includes computational logic, memory implementations and neuromorphic systems. This paper emphasizes the basic properties of memristor at the device level. Different digital circuits have been designed for logic operations and DSP applications. Design methodologies are developed for proper circuit design, and circuit parameters are taken from a very detailed device model and optimization techniques. The transient response of Hybrid CMOS-memristor based logic gates and different adder circuits (i.e, half adder, full adder, carry-save adder) and multiplier circuit are performed in Cadence 180nm technology.

We present a design and protocol to add binary numbers using discrete solitons in waveguide arrays. We show that the nonlinear interaction between discrete solitons in waveguide arrays can be exploited to design half and full adders. By modulating the separation between waveguides and introducing control solitons, we achieve the performance of an XOR gate. We construct the half and full adders using the XOR gate together with the previously- designed OR and AND gates. To facilitate the experimental realization, we calculate the profile of separations between the waveguides that will lead to the performance of the XOR gate.

Enzyme-free and DNA-based universal platform for the construction of various logic devices based on graphene oxide and G-quadruplex

This paper will report the theoretical study and design of optical logic gates and functions using micromechanical phase-shifting gate technology for the first time, and will also cover the proposed fabrication process for these devices. Micromachined phaseshifting gate technology has been used to design micromechanical optical modulators. The basic principle of this technology is to utilize optical interference effects to modulate the light. Since silicon is highly transparent at wavelength of 1.55 micrometers , which is commonly used in optical communication. The phase-shifting gate is fabricated from silicon using standard microelectromechanical systems (MEMS) techniques. The gate is electro-statically or electro-thermally actuated by microactuators integrated on the same chip to realize the modulation of the light. Assume the logic value is 1 when the light transmittance through the gate is bigger than 70%, logic value is 0 when the transmittance is less than 30%. Otherwise, the logic value is undetermined, namely in transition region. Optical logic gates (AND, OR, NOT, etc) and optical functions (Half Adder, Full Adder, etc) can be readily constructed using this technology. The principle of these logic components is modeled, simulated using Matrix Optics Method. Their optimized design and performance is provided using a CAD program based on layered structures developed in MATLAB. Proposed fabrication process for these devices is also included.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Reversible logic preserves information and provides low power computing. Floating point multiplier is an important part of arithmetic in DSP applications. IEEE754 provide two basic and widely used formats for representing floating point numbers namely Single Precision Floating point (SPFP) and Double Precision Floating Point (DPFP). In this paper, we have proposed designs for Reversible SPFP and DPFP point multiplier which requires optimum design of 24X24 and 53X53 multiplying circuitry with reversible gates respectively. Also we presented sign bit calculation and exponent bit calculation circuits by reversible logic. Reversible Mantissa bits calculation circuitry requires consumes more area as it has large value of quantum cost and garbage outputs as compare to reversible sign bit and exponent bits calculation circuitry. So, we mainly focused our work on to minimize the area consumed by the reversible mantissa bits calculation circuit by minimizing the value of quantum cost and garbage outputs of it. In this paper, we presented two ways for partial products generation with reversible gates. We propose a new design of reversible 12X12 reversible Wallace tree multiplier for single precision and double precision mantissa multiplier circuit. Also 5X5 and 5X12 reversible Wallace tree multiplier for double precision multiplier. Here we use the optimized designs of reversible half adder, Full adder and 4:2 compressors. In the final summation stage, we carefully shifted the product terms and add them. For this stage we have carefully chosen the adders and compressor in such way to get the optimized results in terms of quantum cost and Garbage output. We have also shown the improvement in single precision floating point multiplier in terms of Quantum cost and Garbage output.

Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8+T SRAM IMC circuit based on 8+T differential SRAM (8+T SRAM) and proposes 8+T SRAM-based IMC full adder (FA) and 8+T SRAM-based IMC approximate adder, which are based on the 8+T SRAM IMC circuit. The 8+T SRAM IMC circuit performs SRAM read and bitwise operations simultaneously and performs each logic operation parallelly. The proposed IMC FA and the proposed IMC approximate adder can be applied to a multi-bit adder. The two adders are based on the 8+T SRAM IMC circuit and thus read and compute simultaneously. In this study, the 8+T SRAM IMC circuit was applied to the adder, leveraging its ability to perform read and logic operations simultaneously. According to the performance in this study, the 8+T SRAM IMC circuit, proposed FA, proposed RCA, and proposed approximated adder are good candidates for IMC, which aims to reduce energy consumption and improve overall performance.

In this paper, a novel 3-moduli set {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2n+1</sup> − 1,2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2n+1</sup> ,2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2n</sup> − 1}, which has larger dynamic range when compared to other existing 3-moduli sets is proposed. After providing a proof that this moduli set always results in legitimate RNS, we subsequently propose an associated reverse converter based on the New Chinese Remainder Theorem. The proposed reverse converter has a delay of (4n + 6)t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fa</inf> with an area cost of (8n + 2)FAs and (An — 2)HAs, where FA, HA, and t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FA</inf> represent Full Adder, Half Adder, and delay of a Full Adder, respectively. We compared the proposed reverse converter with state of the art converters for similar or equal dynamic range RNS and our analysis indicate that for the same dynamic range the best converter requires (16n + l) FAs and exhibits a delay of (8n + 2)t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FA</inf> . This indicates that, theoretically speaking, our proposal achieves about 37.5% area reduction and it is about 2 times faster than equivalent state of the art converters. Moreover, the product of the area with the square of the delay is improved up to about 84.4% over the state of the art.

This paper gives a newfangled dimension to superconducting logic which is the successor of CMOS logic and other superconducting quantum logic. Reciprocal Quantum logic (RQL) is proposed to achieve the less memory capability. RQL is a modified version of Rapid Single Flux Quantum (RSFQ). We designed and analyzed different RQL logic like half adder, full adder, counter, and Carry Save Adder (CSA) and we achieved an increase in clock speed compared to RSFQ logic by 20%. The designs are made of AndOr and AnotB gate operation and analyzed using WRSPICE software.

A highly functional Si nanodot array device that operates by means of single-electron effects was experimentally demonstrated. The device features many input gates, and many outputs can be attached. A nanodot array device with three input gates and two output terminals was fabricated on a silicon-on-insulator wafer using conventional Si MOS processes. Its feasibility was demonstrated by its operation as both a half adder and a full adder when the operation voltage was carefully selected.