Logic synthesis for PAL-based CPLD-s based on two-stage decomposition

The paper focuses on the methodology of designing a cyber physical systems (CPS) physical layer using programmable devices. The CPS physical layer can be implemented in programmable devices, which leads to a reduction in their costs and increases their versatility. One of the groups of programmable devices are complex programmable logic devices (CPLDs), which are great for energy-saving, low-cost implementations but requiring flexibility. It becomes necessary to develop mathematical CPS design methods focused on CPLD. This paper presents an original technology mapping method for digital circuits in programmable array logic (PAL)-based CPLDs. The idea is associated with the process of multilevel optimization of circuits dedicated to minimization of the area of a final solution. In the technology mapping process, the method of a multioutput function was used in the graph of outputs form. This method is well known from previous papers and proposes optimization of a basic form of the graph of outputs to enable better use of the resources of a programmable structure. The possibilities for the graph of outputs were expanded in the form of sequential circuits. This work presents a new form of a graph that describes the process of mapping and is known as the graph of excitations and outputs. This graph enables effective technology mapping of sequential circuits. The paper presents a series of experiments that prove the efficiency of the proposed methods for technology mapping. Experiments were conducted for various sizes of PAL-based logic blocks and commercially available CPLDs. The presented results indicate the possibility of more effective implementation of the CPS physical layer.

The objective of the technology mapping method presented in this paper is to cover a multiple-output function by a minimal number of PAL (programmable array logic) based logic blocks included in CPLDs (complex programmable logic devices). According to this method, product terms included in a logic block can be shared by several functions. The developed algorithms, implemented within the PALDec system, have been used for partitioning the benchmark circuits due to implementation by means of the PAL-based logic blocks with the restricted number of terms. The results are compared to the classical technology mapping method and synthesis of benchmarks executed by means of MACHXL and MAX+PLUS II software.

Advent of VLSI technology has paved the way for Programmable Logic Devices (PLD), which are widely used as the basic building blocks in high integrity electronic systems. PLDs are considered for their robust features such as high gate density, performance, speed etc. For PFBR Instrumentation and Control systems, PLDs are extensively used to implement digital designs such as VME bus interface logic, control logic and sequencing logic etc. Types of PLDs, such as Field Programmable Gate Arrays, Complex Programmable Logic Devices and Gate Array Logic devices are used in Core Temperature Monitoring System and Safety logics of shutdown systems. Since these devices are reliable as per the manufacturer's specification, they were used in R & D facilities like Fast Breeder Test Reactor and Augmented Boron Enrichment Plant as test beds. However, in order to use PLDs in commercial Nuclear Power Plant (in PFBR), it is vital to know about their performance in other critical applications. The availability of required data is limited, other than for space applications. So, it is proposed to conduct Quantitative Accelerated Life Tests (QALT) for the PLDs. QALT is designed to produce the data required for accelerated life data analysis. This analysis method uses life data obtained under accelerated conditions to extrapolate an estimated probability density function for the product under normal use conditions. Accelerated life tests are conducted on products to understand their failure modes and life characteristics. The products are subjected to enhanced stresses in order to force the products to fail early than they would normally, under use conditions. This process reduces test time. This paper discusses the methodology adapted to perform the Accelerated Life Test for the above mentioned PLDs.

A programmable logic array (PLA) is nonconcurrent if every input pattern selects exactly one product term. We relax this requirement to limited concurrency where all product terms selected by the same input pattern must have identical output parts. A new testing method, OR-k testability, is developed for the on-line (concurrent) checking of limited concurrency PLAs. OR-k testing detects errors due to the selection of one or more extra product terms, and a conventional two-rail parity check on the outputs detects the other errors from single stuck-at, bridging, cross-point and broken line faults. The output patterns of an OR-k testable PLA must be unordered. For such PLAs, certain subsets of the outputs take on an all 1's pattern only in the presence of an extra product term error condition. A limited concurrency PLA tested by OR-k testability is strongly fault secure.

Digital Systems Design with FPGAs and CPLDs

In this paper, the design and development of a pulse-frequency modulation (PFM) signal generator circuit toolbox targeting the programmable logic device (PLD) is presented. PFM is signal encoding scheme that realizes an analog signal level as a digital bit-stream where the bit-stream frequency is proportional to the analog signal level. It is analogous to pulsewidth modulation (PWM). A Python script is run which sets-up a project and the analog signal to encode into PFM. The user can then generate a PFM signal generator circuit description in VHDL for implementation within a field programmable gate array (FPGA) or complex programmable logic device (CPLD). In this paper, the Xilinx Cool runner-II CPLD is chosen as the target device into which the VHDL circuit description can be synthesized and configured into the CPLD. In addition, a MATLAB script is generated to allow for analysis in MATLAB and a SPICE netlist is generated for analog circuit simulation.

A scheme for programmable logic array (PLA) decomposition that consists of one level of PLAs followed by a second level of simple two-input logic gates is presented. The propagation delay is therefore the sum of the delay through one level of PLA and one level of two-input gates. Since the delay through a two-input gate is significantly less than that through a PLA, the timing performance of the new scheme is generally superior to those of earlier PLA decomposition schemes. The sizes of the PLAs used depend on the choice of the two-input gates. An algorithm is presented that chooses the functionality of the gates such that the areas of the first-level PLAs are minimized, further improving performance. The new decomposition scheme was developed for the automatic programming of a programmable logic device (PLD) which had basically a three level architecture. The functional unit for such a PLD is described and the application of the algorithm to the programming of these functional units is discussed. Experimental results show that the new scheme significantly reduces the area over the single PLA implementation. >

We describe a computer aided design (CAD) tool developed to facilitate manufacturing test development for complex programmable logic devices (CPLDs). The CAD tool specifically supports manual and semi-automatic routing for the Cypress Delta 39 K series CPLD for the purpose of manufacturing testing of the programmable interconnect network within the device as well as all programmable logic functions. Two routing algorithms were developed and proved to work correctly with the best one chosen based on complexity analysis. The resultant router CAD tool supports all CPLDs in the Delta 39 K series family and produces the configuration bits necessary to program or configure the CPLD for the extensive tests that must be applied to ensure that the manufactured CPLDs are defect-free. The router has also been used extensively in the verification portion of the design process of the Delta 39 K series CPLDs. While the router is specific to a particular CPLD, the basic approach, including features and algorithms, is applicable to any CPLD or FPGA where programmable routing resources must be specified to accurately test the device and provide design verification.

A collision avoidance system, also known as a pre-crash system, forward collision warning system, or collision mitigation system, is a sophisticated driver-assistance system that aims to avoid or mitigate the severity of a collision. For this research, collision avoidance system will be fabricating to show that this system can detect avoidance range before apply the braking action to prevent collision. The ultrasonic sensor will be used in this system to detect the avoidance range. In this collision avoidance system, there will be uses of Field Programmable Gate Array (FPGA) and Complex Programmable Logic Device (CPLD). This research will observe how to implement FPGA and CPLD in the collision avoidance system using VHSIC Hardware Description Language (VHDL). The VHDL will be done in Quartus II 15.0 Software. In this research, Terasic DE-10 Standard board has been used. It contains FPGA microcontroller model Cyclone V SoC 5CSXFC6D6F31C6N. Max II board is used because it contains CPLD microcontroller model EPM240T100C5.

Recently, numerous efforts have been made on NVM-based Field Programmable Gate Arrays (FPGAs) because the emerging non-volatile memory (NVM) technologies have the advantages of lower leakage power and higher density than Static Random Access Memory (SRAM) technology. However, the cost and the scale of FPGAs are so high and large that they can’t be applied in the consumer electronics field and Internet of Things (IoT). Due to the small scale and low cost, Programmable Logic Array (PLA) is an ideal option for these fields. However, up to now there are few researches on non-volatile PLA based on emerging NVMs. In this paper, a power-efficient non-volatile PLA based on Phase Change Memory (PCM) is proposed. The proposed non-volatile PLA architecture has been evaluated using the 40 nm Complementary Metal Oxide Semiconductor (CMOS) technology, and the simulation results show the correct functionality of the PLA. After the PLA reads the configuration bits from the non-volatile programmable elements (PEs), the power of the programmable elements can be OFF. Therefore, the standby power of the programmable elements is much smaller than that of the commonly SRAM-based PLAs. The simulation results also show that the total power of nvPLA is reduced by about 53.6% when the supply power of Programmable Element is OFF.

Presents a complex programmable logic device (CPLD) based system for cracking the RC4 (Rivest Cipher 4) encryption algorithm. The system achieves an outstanding price/performance ratio, easily beating other low-cost approaches, such as commodity PCs. The system was implemented using a single Altera EPF10K20 CPLD on an Altera UP1 Education Board. This CPLD is large enough to contain the control unit and five functional units. Measured performance on our prototype shows that we can crack a 32-bit RC4 in an expected time of 15 hours (30 hours worst case). This gives a theoretical expected time of 159 days to crack 40-bit keys-the maximum possible key length that can exported from Canada and the USA. Our results demonstrate the effectiveness of programmable logic (CPLD or FPGA) against even a cryptosystem designed for software implementation.

The problem of fault detection and test generation for programmable logic arrays (PLAs) is investigated. The effect of actual physical failures is viewed in terms of the logical changes of the product terms (growth, shrinkage, appearance and disappearance) constituting the PLA. Methods to generate a minimal single fault detection test set (T /sub S/) from the product term specification of the PLA, are presented. It is shown that such a test set can be derived using a set of simple, easily implementable algorithms. Methods to augment Ts in order to obtain a multiple fault detection test set (T /sub M/) are also presented.

Programmable devices containing lookup tables (LUTs) and programmable logic arrays (PLAs) provide a heterogeneous target platform for user designs. Present commercial tools, which target these hybrid devices, require hand partitioning of user designs to isolate logic for each type of logic resource. In this paper, an automated technology mapping tool, hybridmap , is presented that identifies design logic partitions as suitable for either LUT or PLA implementation. A breadth-first search-based subgraph extraction and evaluation heuristic is integrated with product term (Pterm) count, area, and delay estimators to guide the technology mapping process. Hybridmap can be adapted to target a variety of PLA architectures and can accommodate user-provided timing constraints. It is shown that when timing constrained, hybridmap reduces LUT consumption for Apex20KE devices by 8% and when unconstrained by 14% by migrating logic from LUTs to Pterm structures. Hybridmap is shown to outperform previous mapping approaches for Apex20KE-type devices by up to 22%.

Programmable logic arrays (PLA) are highly regular circuits which compute suitable Boolean functions. PLAs are a popular circuit design especially in microcontrollers. PLA folding is a technique for minimizing the area of such PLA. Folding can be formulated in purely graph-theoretic terms. In this paper, we study PLA for a very special class of Boolean functions, namely indicator functions of intervals of binary numbers. As a possible application, we can imagine PLA which shall supervise that an input value lies in a prescribed tolerance interval. From a mathematical point of view, the connection of these interval indicator functions with threshold graphs and cographs is interesting. Our study naturally leads to the folding problem in cographs which is shown to be solvable in linear time. In sections 1-2 we introduce the basic notions. In section 3 we prove a theorem on minimal normal forms of interval indicator functions, thereby motivating the folding problem on cographs. A linear time algorithm solving this problem is derived in section 4. Finally, in section 5, we mention some related results and possible directions of further research.

In order to improve the traditional speed-tension type three-motor synchronous control platform based on PLC bus control to further enhance the speed and control accuracy of the control system, enhance the control effect, Speed-Tension type Three-motor coordinate synchronous control platform based on Multi-microprocessor is proposed in this paper.In this platform, the complex programmable logic devices (CPLD), Digital Signal Processor (DSP) and microcontroller (MCU) are combined.In order to improve rapid and synchronization of the control system, CPLD Parallel nature is used to achieve three serial ports synchronous and concurrency control; Complex control algorithms are implement by the use of DSP fast and efficient data processing capabilities; Experimental results show: The control system is stable, at the same baud rate the control speed of the platform based on multi-microprocessor is more than three times faster than the one of the traditional PLC bus control platform.In the multi-microprocessor control platform， under the same control algorithm regulation time is more fast 0.53 seconds than traditional PLC control platform, the overshoot of the system is 13.53% of the one using traditional PLC control platform, and the tracking the maximum error reduces 60.53% than the one of the traditional PLC control platform.