Low-frequency noise analysis and minimization in Gilbert-cell-based mixers for direct-conversion (zero-IF) low-power front-ends

When an RF carrier is amplified by a GaAs MESFET, amplitude modulation (AM) and phase modulation (PM) noises are imposed on the carrier. This is generally believed to be caused by transposition to the carrier frequency of the low-frequency flicker noise generated by the FET. The cross correlation between the AM and PM noises and the low-frequency noise observed on the drain of the FET is measured. While the AM noise and the low-frequency noise on the drain of the FET exhibit a high degree of correlation, the PM noise and the low-frequency drain noise are not highly correlated. The latter result may explain the limited success of oscillator phase noise reduction methods which rely on the existence of a large cross correlation between the PM and low-frequency noises. >

In this work a discussion on the estimated volume trap densities (NT) compared to surface traps densities (Neff) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise spectroscopy is made. The investigated devices present a fin width of 10 nm, a fin height of 10 nm and four fins in parallel, leading to an equivalent channel width of 120 nm. The equivalent oxide thickness (EOT) is 5.6 nm. More details on the device fabrication and experimental setup may be found in [1,2]. The noise spectra and the estimated surface traps densities are provided in [3]. In this work, focus is only on the identified T4 trap, for which using the linear dependence that should exist between A0i and t0i related to the same trap, without any other assumption, a surface trap density of 2.8∙1012cm-2 is obtained [3]. It should be noted that from the 1/f flat-band noise level an interface trap density value of about 1.9∙1018 eV-1cm-3 is obtained at 300 K.However, as the traps in the Si film are related to a volume phenomenon, two methodologies to estimate the volume trap densities are employed: one using the relationship between the surface trap density and volume trap densitiy [4], where B is a coefficient estimated to be 1/3 [4,5]; and a second one from the temperature (T) evolution at fixed frequency of the Lorentzian plateau level associated to the same trap (from equation 34 in [4]). Using the first method leads to a volume trap density of T4 of about 1.7∙1019 cm-3.The second method consists to use the maximum of the measured Svg_Lor(f 0,T) dependence with temperature. Indeed, the Svg_Lor(f 0,T) of Lorentzians associated to the same trap are proportional with ti(T)/{1 + [2pf 0ti(T)]2}. For a given frequency f 0, if 2pf 0ti(T) ≫ 1, SVg_Lor(f 0,T) ∝ ti(T)]-1, and SVg_Lor(f 0,T) increases with increasing temperature because ti decreases. If 2pf 0ti(T) ≪ 1, then SVg_Lor(f 0,T) ∝ ti(T) and SVg_Lor(f 0,T) decreases with increasing temperature, as explained in detail in [4]. The evolution of the Svg_Lor(f 0,T)∙f 0 in a temperature range where T4 traps are active is illustrated in Figure 1 and presents a bell-shaped behavior, as expected. Using this method, volume trap densities of about 1.25∙1018 cm-3 for f 0 = 10 kHz and of about 1.1∙1018 cm-3 for f 0 = 14 kHz are obtained. It may be observed that the estimated volume trap densities of the T4 defect are about one decade lower than when using the first method. This overestimation by the first method is related to the fact that the theoretical B coefficient was determined for conventional planar devices with one gate [4,5]. Moreover, it may be noticed that the second method is dependent on the fixed f 0 selected.The paper will present a discussion with more details, considering all identified traps in [1] and considering additional new low frequency noise spectroscopy results.References :[1] Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L.-A. Ragnarsson et al., “Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology”, in Tech. Dig. Symp. on VLSI Technology, The IEEE New York, 2018, p.p. 85-86, DOI: 10.1109/VLSIT.2018.8510654.[2] Boudier, B. Cretu, E. Simoen, R. Carin, A. Veloso, N. Collaert, and A. Thean, “Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory and methodology,” Solid State Electron., vol. 128, pp. 102-108, 2017, DOI: 10.1016/j.sse.2016.10.012.[3] Boudier, B. Cretu, E. Simoen, G. Hellings, T. Schram, H. Mertens and D. Linten, “Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs”, In Proceedings of EUROSOI-ULIS’2019.[4] Lukyanchikova, “Noise and Fluctuations Control in Electronic Device”, edited by A. Balandin, American Scientific, Riverside, CA, 2002, pp. 201-233.[5] Yau and C-T. Sah, “Theory and experiments of low-frequency generation-recombination noise in MOS transistors”, IEEE Trans. Electron Dev., 1969, vol.16, pp. 170-177.Figure 1 : SVg_Lor(f 0,T)·f 0 versus temperature for the T4 trap identified in [3]; on the secondary Oy axis the characteristic frequency f 0i of the Lorentzians is displayed in function of temperature. Figure 1

This thesis focuses on the low noise amplifier design of RF receivers for WLAN 802.11a/b/g dual-band and 60GHz applications, in which we cover the topics including introduction to bands and applications, literature review, circuit designs, chips’ measurement results and discussions of the results. There are four chapters to discourse on the basis of low noise amplifier design, and circuit implementations. In Chapter 1, we introduce the wireless RF system, IEEE 802.11 bands, and optical transmission and wireless communications systems development. In Chapter 2, important parameters of LNA are described, including introduction, impedance matching theory, matching network design, noise figure, linearity, and stability. Chapter 3 is focused on the design of a sub 1V CMOS low noise amplifier for dual-band application. This chapter starts from studying three basic topologies for LNA, including their matching design and noise ability. Then we use low voltage characteristics of the folded cascode circuit to design a low power consumption circuit for 2.4GHz/5GHz dual band application. The chip is implemented using TSMC 0.18um CMOS process technology. The measured peak gains are 13.9 dB and 9.6dB at frequencies 2.4GHz and 5GHz, respectively. The measured noise figures are 3.9 dB and 4.7 dB, respectively, for both bands. The power consumption of the circuit is 5.5mW under 1V supply voltage. The subject of Chapter 4 is the 60GHz low noise amplifier design using GaAs process technology, and probing the technology behavior of the GaAs process and its applications. This chip is fabricated using WIN 0.15um pHEMT process. The measured peak gain of this 60GHz GaAs LNA is 11dB at 55.7GHz, and the measured noise figure is 4.8dB. The power consumption of the circuit is 26.6mW under 1.8V supply voltage. In Chapter 5, a 60GHz LNA using TSMC 90nm CMOS process technology is presented. The measurement results show a 6.57 dB gain and a 7.4 dB noise figure at 59GHz. The power consumption of the circuit is 9.4mW under 1.2V supply voltage.

In this paper the theoretical analysis of Low-frequency (LF) noise sources in Optoelectronic Coupled Devices (OCDs) is given and the relation between typical defects and LF noise (1/f noise, generationrecombination (g-r) nosie and burst noise) is described. According to LF noise sources of OCDs and device reliability estimation methods, a novel measurement system based on virtual instrument for OCDs is introduced and nV-level measurement precision can be achieved with the typical LF noise measurement system, which can be used to screen potential devices with excess noise and assess device relibility classifications. In this experiment, the top and bottom limitative thresholds were used to estimate the components parameters of the Power Spectrum Density (PSD) for estimating the reliability of OCDs by the average noise PSD for the 200 OCDs and the classification criterions of electronic components. The experimental results demonstrated that high reliability requirements can be satisfied.

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

Flicker noise in ion-implanted silicon structures

There is the case that the low frequency noise generated complaints of neighborhood residents from the road viaduct. We tried to clarify the source of low frequency noise using the FEM model as one approach for such a problem. First, the 3D-FEM model of the vehicle, bridge, and air was constructed. Then, propagating of the acceleration was calculated by the vehicle traveling on viaduct with road irregularities. Then, the vibration velocity of the viaduct is radiated as sound pressure, and propagating of the sound pressure through the air was carried out by 3D-FEM calculation. Actually, a numerical model for the viaduct that caused the complaint was constructed. The low frequency noise generation mechanism was investigated. The effective measures was considered. As a result, it became clear that a high reduction effect of low frequency noise by performing the measures road irregularities can be obtained in the viaduct. It became clear that there is the acoustic radiation of low frequency noise by the sound insulation wall on the viaduct. By carrying out the parameter study using such a method, we can clarify the occurrence factor of the low frequency noise.

Silicon founders give in their MOS transistor card models some low-frequency noise parameters for SPICE-based circuit simulators corresponding to pure 1/f a or flicker noise, with a very close to unity. MOS transistors used in analogue circuit applications are usually devices with large channel length and width. In low-noise applications, methods such as correlated double sampling are used to suppress the low frequency noise generated by them. Nevertheless, the transistors presently are submicrometre devices exhibiting very different low-frequency noise behaviour. In this paper, experimental low-frequency noise results obtained at room temperature on NMOS and PMOS transistors fabricated using a 0.7 μm process are presented. Both large and small devices on the same process are considered. All regions of operation of transistors are considered. We show that the low-frequency noise behaviour of small area MOSFETs is very different from that of large area devices and that the spectrum is the summation of Lorentzian spectra generated by the switching of individual active traps.

Impact of forward and reverse deep n-well biasing on the 1/f noise of 0.13 μm n-channel MOSFETs in triple well technology

In organic thin-film transistors (OTFTs) the intrinsic properties of the semiconductor are generally masked by structural defects which localize and trap the charge carriers and contact effects, which limit charge injection and cause deviation from ideal linear and square-law behavior. Thus, their electrical characteristics are strongly dependent on the fabrication conditions. We perform current-voltage (I-V) and low frequency noise (1/f) measurements to demonstrate a direct correlation between the thin film microstructure and the performance of OTFTs. Using fluorinated 5,ll-bis(triethylsilylethynyl) anthradithiophene as a model system, we show the relevance of the grain size and grain distribution in the changes in the electronic properties in an OTFT. We present a simple method to induce enhanced grain growth in solution-processed TFTs by room-temperature chemical modification of the source-drain contacts. This leads to improved device performance, and gives an unique thin film microstructure for fundamental studies concerning the effect of structural order on the charge transport. We present evidence that the 1/f flicker noise is sensitive to the microstructure of the organic semiconductor thin film in the transistor channel and can be a diagnostic tool for the quality of the devices.

The carrier transport of p-type low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on flexible substrate has been intensively studied and compared to that on glass substrate in order to improve device performance. To investigate the origin of carrier transport on different substrates, temperature dependent characterizations are carried out for electrical device parameters such as threshold voltage (VTH), subthreshold swing (SS), on-current (Ion) and effective carrier mobility (μeff). The poly-Si grain size Lgrain and the barrier height EB between grain boundaries are well known to be the main parameters to determine transport in polycrystalline silicon and can be extracted based on the polycrystalline mobility model. However, our systemic studies show that it is not grain size but EB that has more influence on the degradation of LTPS TFT on flexible substrates. The EB of flexible substrate is roughly 18 times higher than glass substrate whereas grain size is similar for both devices on different substrates. Compared to the LTPS TFT on glass substrate, higher EB degrades approximately 24 % of Ion, 30 % of SS and 21 % of μeff on the flexible substrate at room temperature. From low frequency noise (LFN) analysis, it is observed that the total trap density (Nt) for flexible substrate is up to four times higher than that of glass substrate, which also supports the high value of EB in the device fabricated on the flexible substrate.

In this work, an in-depth static and low frequency noise characterization of nanosheet FETs, consisting of two vertically stacked silicon channels per device, is performed. A comparison of the performances from n- versus p-channel FETs operated at 300 K and 78 K, in terms of static and low frequency noise parameters variability, is also discussed. The main electrical parameters are estimated from the I-V characteristics using access resistance robust methodologies. An additional criterion demonstrating that the extracted parameters are not influenced by the second mobility attenuation factor is proposed. The low frequency noise studies prove that the dominant flicker noise mechanism is linked to correlated carrier number and mobility fluctuations, with additional access resistances noise contribution in very strong inversion. The importance of the considered total flicker noise model on the estimation of the Coulomb scattering coefficient is highlighted.

A review of recent results concerning the low frequency noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are presented and illustrated through experimental data obtained on advanced CMOS SOI and Si bulk generations. Furthermore, the impact on the electrical noise of the shrinking of CMOS devices in the deep submicron range is also shown. The main physical characteristics of random telegraph signals (RTS) observed in small area MOS transistors are reviewed. Experimental results obtained on 0.35-0.12 um CMOS technologies are used to predict the trends for the noise in future CMOS technologies, e.g., 0.1 um and beyond. For SOI MOSFETS, the main types of layout will be considered, that is floating body, DTMOS, and body-contact. Particular attention will be paid to the floating body effect that induces a kink-related excess noise, which superimposes a Lorentzian spectrum on the flicker noise.

This letter presents the design and measurement of high OIP3, low flicker noise double-balanced Gilbert cell down conversion mixer in CMOS process. The key features of proposed mixer are dynamic current injection and derivative superposition. Since the flicker noise (1/f noise) have a strongly affect mixer's noise figure (NF), a dynamic current injection is used to reduce the flicker noise. The derivative superposition method has an auxiliary common gate stage of radio-frequency (RF) input stage to cancel each third order intermodulation distortion (IMD3) and can provide a high third order output intercept point (OIP3). The proposed down conversion mixer is fabricated in 0.18 μm CMOS technology. And this letter highlights the performances of the proposed mixer in terms of: flicker noise (i.e., noise figure: 5 dB at 100 kHz), third order output intercept point (i.e., OIP3, typically 35 dBm), and the conversion gain (i.e., typ. 17.3 dB) from −20 dBm RF input at 2.4 GHz. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1720–1723, 2016

The concurrent effect of fluorine implantation with various energy and dose on reliability and low-frequency noise characteristics of p-MOSFETs was investigated. The <inline-formula> <tex-math notation="LaTeX">$\Delta $ </tex-math></inline-formula>VT degradation that represents device lifetime of p-MOSFETs with fluorine implantation under negative-bias temperature instability stress was less than that without fluorine implantation. The device lifetimes were improved as the fluorine implantation energy and dose increase. The power law exponent <inline-formula> <tex-math notation="LaTeX">$n $ </tex-math></inline-formula>with the fluorine implantation was larger than that without fluorine implantation. This was related to boron diffusion within the gate oxide because the F atoms enhance the diffusivity of the boron. The difference of flicker noise levels between simulation and measurement data at 1 kHz was much greater than that at 10 Hz, which means that F atoms were mainly located near the Si/SiO₂ interface rather than in the bulk oxide. The fluorine implantation reduced the ID-RTS noise amplitude, which was believed to contribute to the effective passivation of the dominant traps within the gate oxide. Also, the flicker noise was less dependent on implantation energy. But, flicker noise was reduced with increasing implantation dose. Therefore, fluorine implantation is potentially significant for reducing low-frequency noise as well as improving reliability characteristics.