Low-k properties and integration processes enabling reliable interconnect scaling to the 32 nm technology node

Ultra low-k films are used in advanced technologies as dielectric interlayers in Cu interconnects. Due to its high porosity, manufacturing reliable low-k films faces many challenges. This paper discusses the reliability of time dependent dielectric breakdown (TDDB). Degradation of the TDDB lifetime can be observed when there is an abnormal I–V breakdown. Our study characterized the interaction of the breakdown leakage to the etch profile. It has shown that the etch profile weak points have impacts on the TDDB lifetime. By characterizing the Cu etching profile and establishing inline correlations to its TDDB lifetime, a new evaluation method was identified to quickly and precisely reflect the TDDB lifetime performance.

Time-dependent dielectric breakdown (TDDB) in Cu metallization and its dependence on the presence of a barrier metal, the kind of barrier metal, barrier metal thickness, the low-k dielectric and the low-k barrier dielectric, is investigated. There is a distinct difference between TDDB degradation mechanisms with and without barrier metals. The degradation mechanism is drift through the bulk without the barrier, but drift along the CMP surface with the barrier. The barrier property against TDDB is better for Ta and TaN than that for TiN. The TDDB characteristic is independent of the barrier metal thickness, but depends strongly on the electric field strength in the structure. The degradations, related to Cu ion diffusion, are mainly caused by electrical stress, not thermal stress. In a low-k structure, the leakage current path is along the CMP surface due to the electric field concentration. The TDDB lifetime with a barrier metal depends on the breakdown voltage of the low-k material. The TDDB lifetime decreases as the k-value becomes lower. Although the use of low-k barrier dielectrics decreases the TDDB lifetime, a satisfactory TDDB lifetime is achievable with a low-k barrier dielectric as thin as 25 nm. All low-k structures in our study satisfy the 10-year projected TDDB reliability. However, the TDDB lifetime for technology generations beyond the 65 nm-node CMOS may have inadequate 10-year reliability.

We demonstrated an optimization procedure of cell oxide TDDB (time dependent dielectric breakdown) in saddle FinFET. In planar device, oxide time dependent dielectric breakdown is decided by oxide thickness, oxide quality of ISSG (in-situ steam generation), and growth condition. Compared to the planar transistor, the TDDB in saddle FinFET is decided by two parameters - oxide thickness uniformity and conformity in saddle FinFET recess gate bottom, the saddle FinFET shape. In this study of DRAM, the 4G (four giga) consumer grade cell oxide needs to pass 10 years t0.01% TDDB life time. In our work, the outstanding cell oxide t0.01 % TDDB life time in saddle FinFET was introduced. The pristine sample could sustain 7MV/cm oxide strength and over 10 years t0.01% TDDB life time of 80 K (eighty thousand) memory density, but failed (6.58 years) in 4G memory density. The optimized process of in-situ steam growth (ISSG) improves die-to-die thickness variation, providing better cell oxide breakdown time (MTTF) in the three voltage Weibull distribution, which passes 10 years t0.01% TDDB life time as 4G storage memory. The square shape saddle FinFET provides more uniform threshold voltage 3-sigma variation control and less body-effect than the round shape saddle FinFET. The square shape saddle FinFET provides over 500 years t0.01 % TDDB life time as 4G storage memory.

As the industry develops processes for the 65 and 45 nm technology nodes, post etch/ash cleaning faces new challenges with far more stringent requirements on surface cleanliness and materials loss. The introduction and integration of new materials, such as metal hard mask, creates additional requirements for wafer cleaning due to the occurrence of new defect modes related to metal hard mask. These include organometallic residue and metal fluorite compounds precipitating with time. We have developed a novel aqueous solution (AQ) based single wafer cleaning process to address these new defect modes. Physical characterization results and process integration electrical data and reliability data (TEM cross section review of the vias) are presented in this paper.The main conclusions can be summarized as follows: (1) In the dual damascene Cu/low-k process flow with hard mask, there are three typical residues after etch/ash: generic polymer residue, organometallic residue strongly bonded to metal maks, and time-dependent metal fluoride residue. (2) Generic polymer residue is very well characterized [1,2] and is usually easy to remove with solvent or aqueous solution [2,3]. (3)We developed an oxidizing chemistry based process to undercut the hard mask for the organometallic residue removal, which proved highly effective. (4)The time-dependent metal fluoride reside makes queue time control after etch/ash very critical (<1 hour). We developed a process with a fluorine based aqueous chemistry to address the metal fluoride residue, which proved highly effective. With this new process, queue time control is not required. (5) The post etch/ash cleaning for the Cu/low-k structure with metal hard mask typically employs the solvent/dry plasma ash multi-step procedure [4]. The new process developed in this research reduced the multi-step process to one wet clean step with two different aqueous chemistries in sequence. (6) The integration electrical data shows that the new single step aqueous cleaning process performance is comparable to, or even better than that from the solvent/dry plasma ash multi cleaning process. (7) Blanket Cu loss with the new process is about 23A/min, however TEM analysis of the vias after full integration shows Cu loss, we are working to improve the integration related Cu loss.

We studied Cu/low-k integration to test the time-dependent dielectric breakdown (TDDB) reliability of Cu interconnects. We described the TDDB lifetime dependence on SiOC damage caused by sputtering and chemical–mechanical polishing (CMP) processes. The TDDB lifetime of the structure without a cap-SiO layer was three orders of magnitude shorter than that of the structure with the cap layer. However, the film properties of cap-SiO films thinner than 30 nm have a leakage path that allows TDDB degradation to occur easily. We also confirmed that narrowing of intermediate wiring levels with metal-to-metal spacing approaching 100 nm degrades TDDB performance. Moreover, we showed the possibility that chemical attack and mechanical destruction during the polishing cause degradation of TDDB. Optimizing CMP conditions and eliminating the CMP-surface leakage path likely improve line-to-line insulating reliability, such as leakage current and TDDB, because these reliabilities are dominated by the extrinsic failure mode.

This work presents a systematic study of the off-state drain bias time dependent dielectric breakdown (TDDB) mechanism, especially for the short channel transistors in advanced FinFET technologies. The sub-threshold leakage current was found to play a key role in determining the off-state drain bias TDDB degradation. Short channel transistors show higher electric field (E-Field) near the drain side due to increase in sub-threshold leakage current and hence, the breakdown lifetime is seen to scale with decrease in channel length. Moreover, with additional process optimizations, such as source/drain proximity push, the sub-threshold leakage current increases which results in worse off-state TDDB and shorter lifetime during practical circuit stress conditions. Also, impact of body bias on sub-threshold current is also studied in this work.

Bias-temperature stressing of Cu/dielectric/Si capacitors demonstrated that time-dependent dielectric breakdown (TDDB) lifetime strongly depends on dielectric materials. Phosphosilicate glass (PSG) films had much higher immunity from TDDB than thermally grown SiO2. This higher immunity of PSG films is attributed to their greater suppression of Cu diffusion. They provide good protection against Cu contamination of devices. The lifetime (τ) of plasma-enhanced chemical-vapor-deposited TEOS (PECVD–TEOS) films was found to be related to the electric field (E) by using Peek's law (E∝τ-1/4). Using this law, the lifetime becomes rapidly longer than does the previous expectation when the electric field reduces. This suggests PECVD–TEOS films have the potential to be used as interlevel dielectrics for Cu metallization.

As CMOS is being scaled down to 28nm node and beyond, it is necessary to reduce k value in order to improve RC delay. ULK (ultra-low k) (k<2.55) has been implemented into production from 45/40nm node. Compared with low-K film, ultra-low K film is more porous, softer and hydrophilic intrinsically. It is easy to be damaged by plasma, stress, thermal or aqueous environments. It brings more challenges for reliability improvement. This paper focuses mainly on ULK process optimization through simple key parameter optimization to improve voltage break down (VBD) and time-dependent dielectric breakdown (TDDB) and electro migration (EM) performance without scarifying RC delay.

The time dependent dielectric breakdown (TDDB) of four organo-silicate-glass (OSG) films with varying porosity (k=2.0, 2.5, 2.8 & 3.0) was investigated using metal-insulator-semiconductor (MIS) capacitors. Without any barrier, the dielectrics show lower TDDB-lifetimes under Cu ion drift conditions, where the OSG-2.8-film exhibits a better performance. Other results are that the damage caused by TaN/Ta barriers doesn't significantly change the TDDB performance and that the OSG-2.0-film showed excellent TDDB lifetimes.

We have proposed a 65 nm node low stand-by power (LSTP) HfSiON/base-SiO2 transistor design scheme ensuring both high performance and reliability at the same time. In particular, a process condition around the gate was carefully designed. It was found that a low temperature SiO2 offset-spacer could remove the nonintrinsic factor for time-dependent dielectric breakdown (TDDB) without performance degradation. Moreover, a method of monitoring gate leakage after gate dielectric breakdown has been introduced to improve TDDB lifetime. This method can sense extrinsic factors that induce TDDB lifetime degradation. Using this method, we successfully eliminated extrinsic factors that are related to process conditions. Consequently, TDDB lifetime can be guaranteed at Vdd = 1.2 V without performance degradation.

One of the major wearout mechanisms in modern microprocessors is time-dependent dielectric breakdown. Beyond the 28 nm technology node, time-dependent dielectric breakdown from not only the frontend-of-line and backend-of-line, but also the middle-of-line, yields a significant number of failures in VLSI circuits. In this paper, we investigate the impact of time-dependent dielectric breakdown in all phases of fabrication processes (i.e., frontend/middle/backend-of-line) on static random access memory in modern microprocessors. With the analysis of potential resistive short defect locations in a memory cell, we propose a methodology for accurately estimating memory reliability degraded by time-dependent dielectric breakdown. Using activity profiles and device-level wearout models, we also propose a method for statistically estimating the lifetime of a memory cell. Using the simulation methodology, we investigate the lifetime degradation of a memory system while taking all three time-dependent dielectric breakdown mechanisms into account.

Silicon-carbide metal–oxide–semiconductor field-effect transistors (SiC-MOSFETs) are core devices for future power electronics. The factors limiting their automotive applications are currently under investigation. Postoxidation annealing in NO gas is a key technology to achieving high carrier mobility in SiC-MOSFETs. In this article, we study the NO annealing effects on time-dependent dielectric breakdown (TDDB) reliability by the constant voltage stress (CVS) method at room temperature (RT). We show that heavy NO annealing enhances hole trapping near the SiO2/SiC interface and leads to a rapid increase in the gate current ( $I_{\text {g}}$ ) and results in shorter time-to-breakdown ( $t_{\text {BD}}$ ) and smaller Weibull slope of $t_{\text {BD}}$ in comparison to light NO annealing case. However, the detailed examination of the $I_{\text {g}}$ behavior reveals that the charge-to-breakdown ( $Q_{\text {BD}}$ ) and its distribution do not deteriorate. Therefore, we must reconsider the use of the CVS method by examining the $I_{\text {g}}$ behavior during stress, which strongly depends on NO annealing conditions.

The time-dependent dielectric breakdown (TDDB) of Cu damascene interconnects was investigated, noting the time variations in stress-induced leakage current. Copper interconnects normally have symmetric current-voltage curves, which suggests that defects are distributed symmetrically between two Cu lines. Although the impact damage model satisfies this requirement, as does the thermochemical E-model, the Cu diffusion model does not. Without the barrier metal, Cu+ ions rapidly penetrate the dielectric film and form unstable conduction filaments. The leakage current fluctuates greatly due to the rapid Cu movement in the last stage of bias temperature stressing. These current fluctuations also appear in the triangular voltage sweep so that a spurious peak emerges, which is unrelated to the ionic displacement current. The extrinsic TDDB has a small field acceleration parameter (0.5 cm/MV); however, it switches to a large one (4.5 cm/MV) at electrical fields that are higher than 2 MV/cm. Another type of degradation is the thermal reaction between Cu and low-k. High-temperature annealing (&amp;gt;200 °C) generates shallow-energy-level defects in the SiO forbidden-energy gap. The shallow-energy-level defects have less impact on the TDDB lifetime although they cause a large Poole–Frenkel type current.

A novel CoWP cap integration technology for lower leakage current and improved dielectric reliability is proposed for porous low-k/Cu interconnects, NH3 plasma treatment before SiCN deposition reduces leakage current and improves dielectric reliability such as time-dependent dielectric break-down (TDDB) of CoWP capped Cu interconnects. The TDDB lifetime much longer than 10 years is obtained. Moreover, the leakage current less than IE-14A/mm is obtained by low-k top (LKT) dielectric structure combined with the NH3 plasma treatment. In addition, 10% lower RC product is obtained by the LKT structure with CoWP cap

We investigated plasma treatment induced water absorption in a SiOCH low-k dielectric and the influence of the absorbed water components on the low-k dielectric reliability. By using thermal desorption spectroscopy (TDS), water absorption in SiOCH was evidenced for N2/H2 plasma treatments. Based on these TDS results, two anneal temperatures were selected to separate and quantify the respective contributions of two absorbed water components, physisorbed (α) and chemisorbed (β) water, to low-k dielectric reliability. With the physisorbed water desorbed by an anneal at 190 °C, the low-k dielectric shows reduced leakage currents and slightly improved time-dependent dielectric breakdown (TDDB) lifetimes. However, the observed failure mechanism represented by the TDDB thermal activation energy (Ea) does not change until the chemisorbed water component was desorbed by an anneal at 400 °C. The close similarity between Ea and the bond energy associated with the β water component demonstrates that the β bond is among the weakest links for the SiOCH low-k dielectric breakdown.