Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

본 논문에서는 0.15 μm GaAs pHEMT 기술을 이용하여 FMCW(Frequency-modulated continuous-wave) 레이더용 W-band 단일칩 수신기 MMIC를 구현하였다. 제작된 수신기는 4 단 저잡음 증폭기, 하향 변환 혼합기, 3 단 LO 버퍼 증폭기로 구성되어 있다. 수신기의 저잡음 특성과 선형성 향상을 위해 저잡음 증폭기의 성능을 최적화시켰다. 혼합기는 선형성 특성 및 낮은 IF 주파수에서 저잡음 특성을 위하여 저항성 혼합기로 설계하였다. W-대역에서 혼합기를 구동시키기 위해서는 높은 LO 입력이 요구되므로 추가적인 LO 버퍼 증폭기를 설계하였다. 단일칩 수신기의 측정 결과, RF 주파수 f0 GHz, LO 입력 전력 -1 dBm, 그리고, IF 주파수 100 MHz에서, 6.2 dB의 변환 이득, 5.0 dB의 잡음 지수, 그리고, -12.8 dBm의 1-dB 이득 감쇄 입력 전력(P1dB,in) 등의 우수한 특성을 얻었다.

A novel wideband receiver RF front-end, including a resistive negative feedback wideband low-noise amplifier (LNA) with feedforward noise and distortion cancellation and a current commutating down conversion passive mixer with biquad trans-impedance amplifier, is presented in this paper. In comparison to conventional resistive negative feedback LNAs, theory analysis and experimental results for the proposed LNA circuit shows improved performance parameters, including voltage gain, noise figure (NF), and input-referred third-order intercept point (IIP3), especially helpful for wideband LNA design in modern deep-submicrometer CMOS. A wideband receiver RF front-end fabricated in 0.13-μm CMOS, based on the proposed feedforward noise and distortion-cancellation resistive-feedback LNA, has 42-48-dB conversion gain with 0.8-12-MHz tunable IF -3-dB bandwidth and 12-dB adjacent channel selectivity at 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> , -14-dBm IIP3, and 3-dB NF double-sideband with 10-kHz flicker-noise corner frequency.

This paper presents an integrated low noise and highly linear wideband RF front-end circuits for a digital terrestrial and cable TV tuner, which are used as a part of double conversion zero-IF tuner. The low noise amplifier (LNA) shows a low noise figure and high linearity by adopting a noise canceling technique based on current amplification. The up-conversion mixer has high linearity by employing a third order intermodulation cancellation technique. The RF front-end circuits are designed in a 0.18 ¿m CMOS and draw 58 mA from a 1.8 V supply voltage. The RF front-end circuits show a voltage gain of 30 dB, an average single side-band noise figure of 4 dB, an IIP2 of 40 dBm, and an IIP3 of -3 dBm for the entire band from 48 MHz to 862 MHz.

An integrated fully differential ultra-wideband CMOS RF front-end for 6–9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 μm RF CMOS process and achieves a maximum voltage gain of 23–26 dB and a minimum voltage gain of 16–19 dB, an averaged total noise figure of 3.3–4.6 dB while operating in the high gain mode and an in-band IIP3 of −12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

Software Defined Radio (SDR) or Software Radio refers to a class of reprogrammable and reconfigurable radios to support different wireless standards. This paper describes the design of a Wideband Resistive Feedback Low Noise Amplifier (RFLNA) for SDR receivers RF frontend. The design is based on resistive feedback topology. The proposed RFLNA exhibits low noise figure and high gain over the frequency range of 0.8 GHz to 2.5 GHz. This amplifier provides more than 15 dB gain with a gain flatness of less than 0.7 dB and noise figure of less than 1.2 dB over the entire band. The input return loss and output return loss lies within acceptable range. Also, the amplifier is unconditionally stable over the entire frequency range. This frequency range will cover different standards like Global Positioning System (GPS), GSM-900/1800, Universal Mobile Telecommunications System (UMTS), Bluetooth etc.

A low-power fully integrated wideband low noise amplifier (LNA) and down-conversion mixer are designed for direct sequence-UWB (DS-UWB) RF front-end using 0.18-μm CMOS technology. The LNA is designed to cover the full UWB bandwidth of 7.5GHz. Measurements show this LNA achieves gain of 14 16.5dB, noise figure (NF) of 4.2 - 4.8dB and IIP3 of -8dBm, consuming 6mA of current from a 1.8-V supply. The mixer is designed using Gilbert-cell topology to work for both DS-UWB bands. Over both bands, the mixer achieves voltage gain of 4 - 6dB, IIP3 of -1dBm, and NF of 14 to 18dB with a supply current of 11.5mA from a 1.8-V supply.

An inductorless wideband noise-cancelling CMOS low noise amplifier with variable-gain technique for DTV tuner application

The RF front end is generally defined as everything between the antenna and the digital baseband system. For a receiver, it includes all the filters, low-noise amplifiers (LNAs), down-conversion mixers and demodulator needed to process the modulated signals received at the antenna into signals suitable for input into the baseband analog-to-digital converter (ADC), demodulate it and feed with a Transport Stream the Back End part of the system to decode the signal. For this reason, the RF front end is often called the RF-to-TS portion of a receiver. It turns out that this is the most important and critical part of the whole receiver aiming for its good or bad performance. This thesis researched the existing problems that degenerate the analog TV transmission quality; the digital TV tests realized by Mackenzie DTV laboratory comparing the digital TV transmission standards, ATSC, DVB-T and ISDB-T; the proposed and adopted model for the Brazilian Digital TV System; and a proposal of a Front End for the SBTVD that meets the requirements of the system with robustness and flexibility. The Front End was designed, assembled and tested in the DTV laboratory and in the field.

This paper presents a new design of inductorless wideband front-end receiver using 130 nm CMOS technology for LTE bands of 0.7 GHz to 3 GHz. The RF front-end receiver consists of the microstrip antenna, self-bias resistive feedback low-noise amplifier, active balun and folded mixer architecture. The miniature antenna provides good matching results for the entire band of interest. Optimization of low-noise amplifier using linearization technique followed by NMOS switches mixer stage are effectively used to achieve maximum gain, low noise figure, and low power consumption. The designed receiver exhibits a maximum gain of 22 dB, maximum noise figure of 7.5 dB, minimum 3rd order intercept point (IIP3) of −9.2 dBm, and DC power consumption of 22 mW at 1.2 V power supply. Using these optimizations, our proposed receiver can be a good candidate for LTE applications.

Multi-band RF front-ends with adaptive image rejection : a DECT/Bluetooth study case

A noise reduction input matching technique for broadband low noise amplifiers (LNAs) is presented. The proposed LNA employs a positive active feedback network besides of the conventional common-gate (CG) amplifier to achieve both wideband input signal matching and low noise figure (NF), simultaneously. Compared to the conventional broadband noise cancellation techniques, the presented approach achieves the same NF with much less power consumption and high linearity. Circuit level analysis and simulation results are provided to verify the usefulness of the proposed LNA technique. In contrast to the traditional noise cancellation circuit, the proposed LNA does not degrade the linearity and its IIP3 is similar to the simple common-gate LNA. The proposed technique is applied to an LNA operating in 2∼6.5GHz bandwidth.

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

This paper presents a wideband inductorless Low Noise Amplifier (LNA) using a technique for canceling 2nd and 3rd order intermodulation products at the same time and hence achieving high second and third order Input Intercept Point (IIP2 and IIP3) at RF and microwave frequencies. The LNA also makes use of noise canceling stage to achieve low noise characteristics and low noise figure in the whole bandwidth. The LNA was designed in 90-nm CMOS process and consists of a shunt feedback common-source input stage to provide wideband input impedance matching, followed by a noise canceling stage. The common source input stage employs two transistors in parallel biased at different operating regions which perform distortion cancellation. IIP2 and IIP3 of the designed LNA are +41dBm and +2.4dBm respectively. The LNA achieved the voltage gain of 17dB while having the noise figure below 2dB from 500MHz–5GHz.

Software Defined Radio (SDR) or Software Radio is one of the most promising technologies for the mobile and wireless communications. SDR refers to a class of reprogrammable and reconfigurable radios. This paper describes the design of Wideband Low Noise Amplifier (LNA) for SDR receiver's RF Frontend. The proposed Wideband LNA exhibits very low noise figure and high gain over the frequency range of 1.4 GHz to 2.6 GHz. The input and output return loss is found to be less than −10 dB. Also, the amplifier is unconditionally stable over the entire frequency range. This frequency range will cover different standards like Global Positioning System (GPS), GSM-1800, Universal Mobile Telecommunications System (UMTS), Bluetooth etc.

GaN based devices are in great demand due to its rugged characteristics at extreme conditions. In this paper, design of GaN monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) with coplanar waveguide matching is presented to understand the key aspects of high gain, low noise figure and high linearity. The LNA can be used in base station technologies as frequency of interest is from 0.6–3 GHz. It delivers gain of 23 dB and noise figure 0.3 dB and OIP3 upto 51 dBm. The linear performance presented here enables reconfigurable designs of LNA over multiple octaves of bandwidth.