Low power carry lookahead adder by using dependency between generation and propagation

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

This paper presents a comparative research of Carry Lookahead Adder (CLA) carry chains of various design implementations, in terms of propagation delay and transistor count. Two different design implementations of CLA carry generation circuit are discussed and compared based on their speed and transistor count. The representative designs compared are Complementary Metal Oxide Semiconductor (CMOS) Conventional CLA (CCLA) carry generation structure and proposed structure of CLA carry generation, named VpAn. To yield optimized delay for the proposed VpAn Design, transistor resizing has been done. A comprehensive comparison and analysis of performance of four, eight and sixteen bit carry chains are carried out. All the schematics of the CLA carry chains are designed using 0.25um process. The simulations of the schematics of CMOS conventional CLA generation circuits and the proposed CLA carry generation designs are performed using LTspice based on 250nm CMOS technology and 2.5V supply voltage to yield realistic rise and fall times. The speed of each circuit is evaluated and our proposed model reduces the propagation delay by 75% compared to the results of CCLA before sizing. This paper establishes, how the physical implementation of circuits relate to their performance.

Parallel Adders or Ripple Carry Adders (RCA) are the building blocks of the digital processing units. However these RCAs have disadvantage of large propagation delay because of the propagation of carry from the first adder to the last adder. To overcome this drawback, Carry Look Ahead Adders (CLAA) are used. But again these CLAAs consumes more power because of use of large number of gates for generating carry. In this paper, we present a design of CLAA based on hybrid CMOS logic style which consumes less power as compared to the designs of CLAA based on complementary CMOS, Pass Transistor Logic (PTL) and Transmission Gate (TG). The proposed design of CLAA has less propagation delay as compared to its existing designs. Also the number of transistors required for the proposed design of CLAA are less as compared to the existing designs based on other logic style.

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

This paper evaluates the performance of the gate diffusion input technique (GDI) on self-checking and self-resetting logic (SRL) GDI technique of carry select adder (CSA) and carry look-ahead adder (CLA) for different word lengths. In the proposed design adapting level restoration technique eliminates conductance overlap between n-MOS and p-MOS devices. The various self-resetting logic implementations for self-correcting of carry select adder and carry look-ahead adder can detect all single stuck faults in normal operation mode. Besides, two rail encoding technique is used in carry select adder are used for multiple error detection/correction. The SRLGDI setup consists of a pair of full adders, multiplexers, two rail checking, and self-resetting logic. In this technique, the self-checking carry select adder is used for reducing area and self-resetting improves the performance of the adder. The analysis of CSA and CLA with 180nm technology is simulated by using Cadence tools. The delay reduction is 12.836% for 8-bit CLA using SRL GDI, power reduction is 27.55% for 8-bit CSA using SRL-GDI compared to the gate diffusion input technique. This GDI technique implementation saves the average energy consumption up to 31.14% in CSA and 32.83% in CLA making it suitable for power optimization in high speed VLSI systems.

Objective: The Ultimate aim of the VLSI Design is to improve the efficiency, Reduction of Delay and Power Consumption and to minimize the area. In our proposed approach we had implemented the analysis had been done on the field of Speed, Power consumption, Area and Power delay product (PDP) for a carry skip adder with other adders listed as the parallel prefix adders and others. Methods/Statistical Analysis: The Carry-Skip Adder planned here reduces the time required to propagate the carry by skipping over teams of consecutive adder stages, is understood to be comparable in speed to the carry look-ahead technique whereas it uses less logic space and fewer power. Findings: The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Simulation results also shows that the proposed adder Architecture is Faster and Area efficient compared to other existing adder architecture. Application/ Improvements: They estimate the performance of proposed design will be better in terms of Logic and route delay by experimental results. Keywords: Adders, Carry Bypass Adder (CBA), Carry Increment Adder (CIA), Carry Look-Ahead Adder (CLA), Carry Skip Adder (CSkA), Han Carlson Adder (HCA), Ripple Carry Adder (RCA)

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.

A carry look-ahead adder (CLA) is a digital circuit which is used widely used in any electronic computational device to improve speed calculation by reducing the time required to define carry bits. Despite the fact that CLA is used massively in modern digital systems, there is no online tool to automatically generate the HDL description. For this reason we developed a cloud based tool to automate the design of optimized CLA and provide custom testbenches to verify their correctness for singed and unsigned numbers. It is also can be used by the students to create and understand deeply the way CLA works.

A finite impulse response (FIR) programmable filter is implemented using computation sharing multiplication (CSHM) technique to reduce power consumption and improve performance. Both carry select adders (CSLA) and carry look-ahead adders (CLA) are used to determine power consumption, throughput and area of the proposed design. A 10-tap programmable FIR digital filter was implemented in CMOS 180 nm technology and a maximum clock frequency of 1.42 GHz was achieved. The area is determined to be 516 K transistors with latency of 131 clock cycles and power consumption of 2.966 W.

Conventional CLA adder has has a large number of transistors and high input impedance, which affects various performance aspects, resulting in high delay and power consumption. Therefore, to increase the performance and reduce delay, several optimized structures of CLA are proposed. From the perspective of structure and power, this paper selects four different design schemes and uses Cadence Virtuoso 90nm technology to compare and analyze the optimization results in aspects of circuit area, delay and power consumption. The analysis results show that the conventional 4-bit adder structure can be improved by designing the carry term Field Effect Transistor (FET) network and replacing the existing gate circuit with a hybrid Gate diffusion technology (GDI) gate, which can reduce the number of transistors and the design circuit area. They also contribute to improving the power consumption, delay, power delay product (PDP) and other performance parameters. Pipeline technology and multi-layer CLA block technology are suitable for carry look-ahead adder with more bits and longer carry chain, which can shorten carry propagation time, further optimize processor performance and improve CPU computing efficiency.

Multiplication is one of the most basic processes, in digital signal processing applications. To process the instructions, most processors require multiplication. Because multipliers are employed in almost all arithmetic operations, they consume the majority of time and power. As a nutshell, the multiplier's efficiency is critical in terms of enhancing processor performance. The array multiplier is one of the most efficient multipliers since it is both quick and simple. However, power consumption is high. The basic components of an array multiplier are adders. The multiplier's efficiency will improve if the adders are much more efficient. The prior study used Complementary Metal Oxide Semiconductor (CMOS) to construct a Quaternary Carry-Lookahead Adder (CLA) that substitutes the adder circuit in the array multiplier. Quaternary number system circuits are quicker than binary number system circuits and can execute arithmetic operations without carry. However, Quaternary circuits take up more space. As a solution, the Quaternary Carry Increment Adder (CIA) is proposed. The proposed adder consumes less power and occupies less area than the existing Quaternary CLA. In the array multiplier, the Quaternary CIA substitutes the Quaternary CLA. This helps to lower the multiplier's power and area consumption. Tanner EDA tool is used to designing the circuits and were simulated with 180 nm technology. Various parameters such as delay, power and power-delay product of the existing and the proposed are measured and compared.

This paper compares several designs of spanning tree adders for 16 and 32 bit widths. The carry select part of the spanning tree is done using ripple carry and carry skip adders (4, 8 and 16 bits) and compared in terms of delay, complexity and power consumption. The spanning tree design is also compared with that of a conventional carry lookahead adder. All the designs are done using only 2 input NAND and NOR gates and inverters in 0.18 μm CMOS technology. The delay and power consumption is determined by use of simulations performed with Synopsys and Cadence design tools. The spanning tree adder realized with carry skip adders is about 40% faster than the carry lookahead adder with an approximate increase of 17% in complexity and 22% in power.

A novel self-checking carry lookahead adder with multiple error detection/correction

For continuous real-time monitoring of personal health, wearable devices are indispensable. The constraintsof cost, power consumption, and limited device dimensions are the critical issues which need to be handled carefullywhile designing these battery-powered devices. The wearables employ high-end processors dedicated for complex signalprocessing. The core of every digital signal processor is its data path. The arithmetic units like adders constitute thecore of data path and addressing unit. This work proposes a novel low-complexity asynchronous pipelined adder. Theproposed design guarantees great savings in power and latency, which makes it a suitable candidate for low-power high-speed sophisticated wearables. The proposed design consumes a minimum power of 33.46 ?W and offers a minimumpropagationdelayof 0.04ns incomparison tostate-of-artadders suchas ripplecarry adder(RCA),carry lookahead adder(CLA), and carry select adder (CSA). Thus, an area-delay-power efficient adder design guarantees high-end performancefor wearables.

SUMMARY This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.