Optimization of spanning tree adders

Adders are digital circuits that perform addition operation. There are various types of adder structures such as Ripple carry adder (RCA), carry look ahead adder (CLA) , carry select adder (CSLA) , carry save adder(CSA), carry skip adder, carry increment adder and so on. Again CSLA is of two types that is linear carry select adder (LCSLA) & square root carry select adder (SQRT CSLA). To design an efficient adder circuit in terms of area, power and speed is one of the challenging task in modern VLSI design field. In this paper performance analysis of different adder structures like RCA, CLA, LCSLA and SQRT CSLA has been carried out and then a Heterogeneous adder structure is proposed, which compose of four different sub homogeneous adders (RCA, CLA, LCSLA and SQRT CSLA). The heterogeneous adder structure is used to demonstrate the tradeoffs between the speed and area. In this paper, all adder structures i.e., RCA, CLA, LCSLA and SQRT CSLA are to be designed and are to be compared with each other in terms of delay and area. Then by using the homogeneous adder structures different heterogeneous adder structures of 16-bit size are to be designed. Different heterogeneous adder architectures are compared with each other in terms of delay (ns) and area (number of LUTs). All the adder structures are designed using VHDL with the help of ISE Xilinx design suite 14.2 and functionally simulated using ISIM simulator. All the designs are to be synthesized using Xilinx XST synthesizer.

Objective: The Ultimate aim of the VLSI Design is to improve the efficiency, Reduction of Delay and Power Consumption and to minimize the area. In our proposed approach we had implemented the analysis had been done on the field of Speed, Power consumption, Area and Power delay product (PDP) for a carry skip adder with other adders listed as the parallel prefix adders and others. Methods/Statistical Analysis: The Carry-Skip Adder planned here reduces the time required to propagate the carry by skipping over teams of consecutive adder stages, is understood to be comparable in speed to the carry look-ahead technique whereas it uses less logic space and fewer power. Findings: The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Simulation results also shows that the proposed adder Architecture is Faster and Area efficient compared to other existing adder architecture. Application/ Improvements: They estimate the performance of proposed design will be better in terms of Logic and route delay by experimental results. Keywords: Adders, Carry Bypass Adder (CBA), Carry Increment Adder (CIA), Carry Look-Ahead Adder (CLA), Carry Skip Adder (CSkA), Han Carlson Adder (HCA), Ripple Carry Adder (RCA)

Performance optimization of the nano-scale carry-skip adder based on quantum dots and its application in the upcoming Internet of Things

Adders play a central role in arithmetic computations as well as digital signal processing. Besides addition, adders are used in multiple operations in processors. Based on our requirements upon variegated parameters our choice on adders can also be changed. Most digital systems, such as processors or computers, have 32-bit architecture, which includes 32-bit integers, registers, and memory locations, among other things. As a result, optimising 32-bit adders minimises total latency and thus enhances speed. In this work, performance analysis of 32-bit adders is compared by the Verilog programming language. 32-bit adder design is highly crucial as its architecture is widespread and used widely, and it is so hard to design. Designing several adders of 32 bit such as carry save adder (CSA), carry look ahead adder (CLA), ripple carry adder (RCA), modified carry select adder (MCSA), carry skip adder (CSKA), kogge stone adder (KSA) and carry select adder (CSLA), are explained in this work based on memory usage and delay. Discussions on adder types are made that aids in reducing the time usage on tedious tasks. CLA and CSKA were compared. Synthesis and simulation are done using Xilinx ISE tool. The simulation results help in the determination of the attributes that were assorted.

Realization of processing In-memory computing architecture using Quantum Dot Cellular Automata

We present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This grouping reduces active power by minimizing extraneous glitches and transitions. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. Compared to previous designs, the adder architecture decreases power consumption by reducing the number of transistors, logic levels, and glitches. A 32-bit carry skip adder design that uses our approach has been implemented in 130 nm CMOS technology. At 1.2 V and 25 C, the 32-bit adder has a critical path delay of 921 ps and average power dissipation normalized to 600 MHz operation of 0.786 mW. We also present a technique to quickly perform saturating addition, which is useful in a variety of digital signal processing and multimedia applications. Our technique for fast saturation is based on techniques for carry select addition and works particularly well when the input and output operands can have different formats. A 40-bit carry skip adder that uses our technique for fast saturation has critical path delays of 1149 ps in 130 nm technology at 1.2 V and 25 C and 560 ps in 90nm technology at 1.0 V and 25 C. The 40-bit adder's average power dissipation normalized to 600 MHz operation is 0.928 mW in 130 nm technology and 0.335 mW in 90 nm technology.

Addition is an indispensable operation for any high speed digital system, digital signal processing or control system. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. In this work technology independent logic optimization is used to design 1-bit full adder with 20 different Boolean expressions and its performance is analyzed in terms of transistor count, delay and power dissipation using Tanner EDA with TSMC MOSIS 250nm technology. All the Boolean expressions are realized in terms of CMOS logic. From the analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.

This paper presents a comparative research of Carry Lookahead Adder (CLA) carry chains of various design implementations, in terms of propagation delay and transistor count. Two different design implementations of CLA carry generation circuit are discussed and compared based on their speed and transistor count. The representative designs compared are Complementary Metal Oxide Semiconductor (CMOS) Conventional CLA (CCLA) carry generation structure and proposed structure of CLA carry generation, named VpAn. To yield optimized delay for the proposed VpAn Design, transistor resizing has been done. A comprehensive comparison and analysis of performance of four, eight and sixteen bit carry chains are carried out. All the schematics of the CLA carry chains are designed using 0.25um process. The simulations of the schematics of CMOS conventional CLA generation circuits and the proposed CLA carry generation designs are performed using LTspice based on 250nm CMOS technology and 2.5V supply voltage to yield realistic rise and fall times. The speed of each circuit is evaluated and our proposed model reduces the propagation delay by 75% compared to the results of CCLA before sizing. This paper establishes, how the physical implementation of circuits relate to their performance.

The speed of an adder is a significant factor in the performance for any arithmetic circuit. This paper primarily evaluates four different 4-bit adder architectures on 28nm technology in terms of speed. However, the performance of the adders is analysed based on delay, power dissipation, leakage current and area. The purpose of our work is to analyse the designs of the 4-bit adders, so as to give a better understanding as to which adder is suitable to the designer. The 4-bit adders, namely ripple carry adder (RCA), carry lookahead adder (CLA), carry skip adder (CSK) and Manchester carry chain adder (MCC), are designed using Cadence Virtuoso on 28nm technology. They are simulated and analysed at various supply voltages ranging from 0.6 to 1 V using ELDO tool. The results show that at 0.6 V CLA is faster than CSK by 27.9%, MCC by 8.2% and RCA by 26.46%.

In the recent decades, the demand of mobile electronic devices is exponentially increased which creates a urge to design highly effective VLSI structures. The operations in the devices necessitate to be computed by low-power, area-efficient designs which operates at higher speed. Addition is the commonly used arithmetic operation; and adder is the basic arithmetic element of the processor. Presently, Carry Skip adder (CSKA) is found to be an effective adder which is compact and consumes less power. But, the lower speed of CSKA became a major drawback and it fails to employ in high-speed applications. To overcome the limitations of CSKA, a faster and efficient Parallel Prefix Adder (PPA) is introduced, which is developed from the carry look ahead adders. In this paper, we design and develop a new PPA architecture namely Kogge Stone adder (KSA) for 8, 16, 32 and 64-bit addition. The proposed method is implemented and the results are compared with CSKA interms of area, delay, speed and power consumption. Simulations results on Kogge Stone adders (KSA) reveal minimization of power consumption compared with the CSKA along with area compaction and high speed.

According to recent research, with the ever-increasing use of Internet of Things (IoT) devices, there has arisen an ever-growing need for high-performance yet low-power circuits that can efficiently process information. Quantum-dot Cellular Automata (QCA) has emerged as a promising alternative to conventional complementary metal-oxide-semiconductor (CMOS) technology due to its great potential in digital design at nanoscale levels on account of very low power consumption and very high processing speed. However, QCA circuits are inherently prone to faults due to variations in manufacturing processes and due to the influence of environmental factors. These faults degrade the performance of a QCA circuit considerably. Hence, fault tolerance is one of the major factors of consideration while designing a QCA circuit, particularly when the application requires very reliable and continuous operation, say in an IoT system. As such, this work presents a fault tolerant Carry Skip Adder (CSA) for QCA-based circuits. The fault tolerance of basic arithmetic components of IoT nodes performing tasks corresponding to the signal processing, control, and data manipulations is enhanced in the proposed architecture. The area occupied by a fault-tolerant full-adder circuit is 0.06 μm² and a clock cycle is 0.75; its core will be used in the CSA design. It realizes fault-tolerant multiplexers (MUX) and a majority gate, which gives the same result when there is a missing or extra single-cell fault. The most astonishing characteristic of this transistor-based CSA is its 85% tolerance for different types of failures. The CSA with three layers contains 1542 quantum cells, 4.75 clock phases, and occupies an area of 4.59 μm². It is compact and efficient architecture; therefore, it is very suitable for IoT applications where the area constraint and power efficiency are the key issues. The proposed CSA will increase the robustness and reliability of QCA-based digital circuits by integrating fault tolerance into its design such that the circuitry based on QCA can keep their functionality on even in fault-prone environments.

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

In digital systems design, the high-speed adders play an imperative role in modules like adders, multipliers, division, etc. to obtain the results quickly. In digital signal processor and computer data path circuits, carry look-ahead adder (CLA), carry save adder (CSA), carry select adder (CSeA) and carry skip adder are the mostly used fast adders to improve the performance of a system. This work mainly emphasizes on fault-tolerant carry save adder using hardware redundancy configurations for the betterment of reliability at the cost of area. The popular methods like dual (DMR) and triple modular redundancy (TMR) are implemented to detect only but not correct an error and tolerate single event upset (SEU) error respectively. To tolerate multiple errors, for example, two, three and four errors, the 5-modular (quintuple), 7-modular (septuple), and 9-modular (nonuple) redundancy configurations are used respectively. For experimental results, the implementation of a simple addition of four 4-bit numbers is considered on Altera FPGA EP4CE115F29C7 device using Quartus II synthesis software tool. Simulation results reveal that for example in nonuple MR, CSA using CSeA final stage obtain higher performance (45.7 MHz) with moderate power dissipation as 173.36 mW and at the cost of more LEs (216).

The superpipelining concept is applied to adder designs. Superpipelined designs of ripple carry, carry select, conditional sum, and carry lookahead adders are presented as examples. It is shown that the carry skip adder cannot be superpipelined. Results for the total number of latches required, the number of pipelining stages, and the total gate counts are presented. It is shown that the superpipelined carry lookahead adder is faster and less complex than the other adders.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>