Low power circuits and microarchitectures for gigascale integration

The growth of battery-powered mobile and wearable devices has increased the importance of low-power operation and cost in system-on-a-chip (SoC) design. Supply-voltage scaling is the predominant approach to active power reduction for SoC design, including voltage scaling for on-die memory given increasing levels of memory integration. SRAM can limit the minimum operating voltage (V MIN ) of a design, often leading to the introduction of separate voltage supplies for on-die memory. Additional supplies increase platform cost, and operating memory at higher voltage leads to increased power consumption. The introduction of trigate devices at the 22nm technology node delivered superior short channel effects and subthreshold slope relative to existing bulk planar device technology enabling reduction in threshold voltage within a fixed leakage constraint. Lower transistor V th , improvements to random device variability, and assist circuits to overcome device-size quantization enabled a >150mV reduction in SRAM V MIN [1]. At the 14nm technology node, FinFET device-size quantization remains a challenge for compact 6T SRAM bitcells with minimum-size transistors. Careful co-optimization between technology and design of memory-assist circuits is required in order to deliver dense, low-power memory operation at low voltages. In this paper, we present an 84Mb SRAM array design with wide-voltage-range operation in a 14nm logic technology featuring 2nd-generation FinFET transistors.

VLSI system performance increased by five orders of magnitude in the last three decades, made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize complex architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill will continue, providing integration capacity of billions of transistors; however, power, energy consumption, and variations will be the barriers. Performance at any cost will not be an option in the future; VLSI systems will have to emphasize performance delivered in a given power envelope, with complexity limited by energy efficiency and variability. This talk will discuss potential solutions in process technology, circuits, and microarchitectures to exploit future gigascale integration capacity. The system on a chip (SOC) concept will help integrate diverse functional blocks, providing valued performance. The talk will conclude with recommendations to the VLSI system designers and microarchitects on how to exploit these emerging paradigms.

This paper proposed a low-dropout regulator (LDO) with a dynamic-biasing super buffer technique and a 2-stage error amplifier (EA). The 2-stage EA provides a high loop gain and wide output swing so as to implement an ultra small load regulation and line regulation. The dynamic-biasing super buffer technique, made of super source follower, ultra low-output impedance buffer and dynamic biasing technique, ensures the stability of the LDO with a 1-μF output capacitance and adjusts the quiescent current (Iq) of the LDO in different load current so that an ultra low I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">q</sub> is achieved by the proposed LDO structure. Based on Global Foundry 0.18-μm CMOS process, the circuit can drive up to 200-mA load current at 1.2-V output voltage in 1.4-V- 2-V supply voltage (Vs). In 1.4-Vs, Iq is 26.3-μA in no load and 57.7-μA in full load. In 2-Vs, Iq is 26.4-μA in no load and 246.2-μA in full load. The load regulation is 1.12-μV/mA in 1.4-Vs and the line regulation is 0.50-mV/V in 200-mA full load.

The System-on-Chip (SoC) design paradigm has revolutionized modern electronics by integrating an entire system into a single chip.SoCs combine various components like processors (CPU/GPU), memory, I/O interfaces, and peripheral units into one compact module, significantly reducing the size, cost, and power consumption of electronic devices.This seminar will explore the fundamental principles behind SoC design, its architecture, and key components, focusing on both the theoretical concepts and practical implementation strategies.We will delve into the design methodology of SoCs, examining top-down and bottom-up approaches, system integration, and verification.

Integrated circuits operating in the near/subthreshold region offer low energy consumption. However, due to the constrained voltage scalability of SRAMs, efficient power delivery is difficult to achieve. A traditional implementation would require at least two distinct voltage supplies generated by possibly two power converters. In this article, a new implementation for near/subthreshold operation is presented. The proposed implementation consists of a new “converter-free” design based on a three-level voltage stack operating at 1.8 V ± 5%. Here, the leakage current from the SRAMs in the top stack is recycled to sustain the near/subthreshold operation of the logic circuits in the two lower stacks. A test chip with the proposed voltage-stacking technique was implemented in a 28-nm low- Vth (LVT) fully depleted silicon on insulator (FDSOI) technology. The test chip is an ultralow-power advanced system-on-chip (SoC) consisting of an RISC-V core, a coarse-grained reconfigurable accelerator, and peripherals. The SoC uses a current sink and an adaptive body-bias controller for voltage regulation of the intermediate voltage rails between the stacks. The proposed system achieves up to 95% power delivery efficiency with negligible area overhead (~ 1%). The silicon measurement shows that the system energy efficiency is improved by 1.6× on average, and the energy consumption is reduced by 37% on average compared to the flat implementation.

A 6.6 mW 1.25–2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO

During fabrication process, mixed analog and digital integrated circuits (ICs) are more susceptible to process variations and physical defects than pure digital ICs. Therefore, it is beneficial to simulate the effects of process variations and defects on mixed-signal designs even before the design goes into production. Simulations of ICs having process variations are performed with Monte Carlo simulations. And, simulations of ICs having physical defects are called fault simulations. However, both simulation schemes require large numbers of instances. Consequently, simulation times can be extremely long, e.g. hours or days. In this System-on-a-Chip (SoC) era, mixed-signal designs are becoming more complex and thus impossible for traditional simulation schemes to be effectively applied. To dramatically reduce Monte Carlo simulation time and fault simulation time, a new behavioral simulation approach is proposed in this dissertation. Essentially, timing consuming detailed circuit simulations can be replaced by simple linear equations. A flash analog-to-digital converter (ADC) is used here to demonstrate the feasibility of proposed approach. The behavioral models for the flash ADC having process variations and physical defects are built. With these behavioral models, behavioral simulation programs are written in C++ to perform fast Monte Carlo simulations and fault simulations. For the small 3-bit flash ADC, the proposed method reduced the Monte Carlo simulation time, with 30 instances, from 180 hours to a mere 15 minutes. Such dramatic reduction in simulation time was achieved with a maximum prediction error of no more than 6%.

Technology scaling into subnanometer range will create process variations which have impact on the overall manufacturing yield and quality. At the same time System-on-Chip (SoC) complexity and communication requirements are increasing which will make a SoC designer goal to design a fault-free system a very difficult task. The dependability will be an important measure of System-on-Chip design process. As a result we see a shift from bus based systems into networked systems and from traditional Register Transfer Level (RTL) design paradigm into higher abstraction levels — High Level Synthesis (HLS) and system-level design. In real-time networked systems the dependability cannot be reached effectively without predictable contention free communication synthesis. In this paper, an approach that takes into account flow control unit(s) transmission latencies over actual links, is extended to cover, in addition to virtual cut-through, also wormhole switching and wormhole switching with virtual channels. The communication synthesis results are used in our proposed system-level design methodology for dependable realtime Systems-on-Chip.

This paper presents a power delivery monitor (PDM) peripheral integrated in a flip-chip packaged 28 nm system-on-chip (SoC) for mobile computing. The PDM is composed entirely of digital standard cells and consists of: 1) a fully integrated VCO-based digital sampling oscilloscope; 2) a synthetic current load; and 3) an event engine for triggering, analysis, and debug. Incorporated inside an SoC, it enables rapid, automated analysis of supply impedance, as well as monitoring supply voltage droop of multi-core CPUs running full software workloads and during scan-test operations. To demonstrate these capabilities, we describe a power integrity case study of a dual-core ARM Cortex-A57 cluster in a commercial 28 nm mobile SoC. Measurements are presented of power delivery network (PDN) electrical parameters, along with waveforms of the CPU cluster running test cases and benchmarks on bare metal and Linux OS. The effect of aggressive power management techniques, such as power gating on the dominant resonant frequency and peak impedance, is highlighted. Finally, we present measurements of supply voltage noise during various scan-test operations, an often-neglected aspect of SoC power integrity.

Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.

System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.

While silicon scaling makes possible highly integrated SOCs for function rich electronic products, the efforts required to design such an SOC has increased more rapidly than the transistor complexity of the SOC itself. At the same time, market competitiveness continues to demand feature differentiation and short TTM (time-to-market) for the high volume electronic products. This paper describes the emerging methodology of using configurable processors as the building blocks for complex SOC designs. Using processors to replace hardwired logic to accelerate hardware design and bring full chip-level programmability. Using configurability to deliver domain-specific efficiency, high throughput, low cost and low power dissipation. Configurable processor technology has made the creation and adoption of these tuned processors easy. Configurable processors have been used in a variety of high volume SOC platforms and adopted by market leaders. This paper also includes product examples.

Each new generation of smartphone gains capabilities that increase performance and power efficiency allowing us to use them for increasingly complex calculations such as Deep Learning. This paper implemented four Android deep learning inference frameworks (TFLite, MNN, NCNN and PyTorch) to evaluate the most recent generation of System On a Chip (SoC) Samsung Exynos 2100, Qualcomm Snapdragon 865+ and 865. Our work focused on image classification task using five state-of-the-art models. The 50 000 images of the ImageNet 2012 validation subset were inferred. Latency and accuracy with various scenarios like CPU, OpenCL, Vulkan with and without multi-threading were measured. Power efficiency and realworld use-case were evaluated from these results as we run the same experiment on the device's camera stream until they consumed 3% of their battery. Our results show that low-level software optimizations, image pre-processing algorithms, conversion process and cooling design have an impact on latency, accuracy and energy efficiency.

The recent demand for system-on-chip RF mixed-signal design and aggressive supply-voltage reduction require chip-level accurate analysis of both the substrate and power delivery systems. Together with the rising frequency, low-k dielectric, copper interconnects, and high conductivity substrate, the inductance effects raised serious concern recently. However, the increasing design complexity creates tremendous challenges for chip-level power-delivery substrate co-analysis. In this paper, we propose a novel and efficient reluctance-based passive model order reduction technique to serve these tasks. Our work, SuPREME(Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation) not only greatly reduces the computational complexity of previous reluctance-based model order algorithms but is also capable of handling large number of noise sources efficiently. To facilitate the analysis of inductive substrate return paths and evaluate the high-frequency substrate coupling effects, we derive a novel RLKC substrate model from Maxwell's equations for the first time. Experimental results demonstrate the superior runtime and accuracy of SuPREME compared to the traditional MNA-based simulation.

This paper analyzes the impact factors on power delivery capability and efficiency in switch-inductor-inductor-diode (SLLD) capacitive-coupled wireless power transfer (C-WPT). A new varying resonant frequency (VRF) control is introduced to improve output voltage level and power delivery over the performance of a traditional fixed resonant frequency (FRF) control. Also, it is proven that using high dielectric material as insulation material for the capacitive coupling can provide high power delivery and efficiency over a wide range of distance in C- WPT applications. These results were verified by simulation studies and experimental tests on a hardware testbed.