Low-power design by hazard filtering

Metal Oxide Thin Film Transistors (MO TFTs) have garnered considerable interest in emerging Internet of Things (IoT) fields such as wearable electronics, displays, Radio Frequency Identification (RFID), and biomedical monitoring, owing to their flexibility and transparency. However, limitations in channel materials make MO TFT-based circuits unipolar. Unipolar circuits often exhibit elevated short-circuit power consumption, which restricts the development of MO TFTs in the IoT sector. This paper introduces a Capacitively Coupled Near-Threshold Biasing (CCNB) technique that leverages the unique Capacitance-Voltage (C-V) characteristics of MO TFTs to bias devices in the near-threshold region, achieving nearly a 95% reduction in power consumption compared to traditional designs with the device coupling ratio (channel capacitance/overlap capacitance) at 40. Furthermore, considering the significance of clock signals in IoT applications, we have also developed a low-power full-swing Ring Oscillator (RO) based on our CCNB technique, resulting in a 90% reduction in power consumption and a nearly 70% reduction in PDP compared to conventional low-power designs.

The drive for ultra efficient and low-cost portable devices continues to push the need for low power circuit designs. The increasing transistor density and complexity of IC designs aggravates the task of producing efficient low power and low cost design. The short time to market (TTM) also increases this burden on designers, as optimal designs have to be produced in an ever decreasing amount of time. This paper presents an optimization design flow methodology that optimizes the power (accounting leakage) consumption of integrated circuits (ICs). The design flow incorporates a stochastic gradient descent (SGD) based algorithm and is implemented using a 45 nm thermal sensor circuit as case study. Power-efficient high-sensitive thermal sensors are important to reduce the burden on the systems or circuits that they are implanted to sense. Experiments are performed to apply the proposed design flow methodology on the thermal sensor with the power consumption as the design objective while keeping the temperature resolution as a constraint. Experiments on full-blown (RCLK) netlist of sense amplifier show a reduction in power consumption by 38%.

New complex and Low Power systems are being implemented using advanced Electronic Design Automation (EDA) tools. Low power designs are not only used in small size applications like mobile phones, tablets and handheld devices but also in high-performance computing applications. As the complexity increases day by day, the dissipation of power has emerged as one of the very important design constraints. In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the Flip-Flop is an important element to determine the performance of the synchronous circuit. In the research of low power and low voltage VLSI circuits, the use and implementation of Dual Edge Triggered Flip-Flop (DETFF) has gained more attention at the gate level design. The main advantage of using DETFF is that it allows one to maintain a constant throughput while operating at only half the clock frequency. In this paper, a dual-edge triggered sense amplifier flip-flop is designed for low power systems. For DETFF, the optimal delay, power consumption, and energy are determined as the primary figures of merit. The use of dual edge-triggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed.

Both the capacity and the complexity of modern FPGA devices increase rapidly. Also, it is common that battery-powered embedded systems are equipped with FPGA devices. Therefore, reducing the power consumption of FPGA devices has become a very crucial issue. Not only dynamic power consumption but also leakage power consumption increases as the feature size to manufacture FPGA devices shrinks. To reduce the power consumption of FPGA devices, carbon-nanotube field effect transistor (CNFET) has emerged as a promising candidate for replacing silicon metal oxide semiconductor field effect transistor (Si-MOSFET). In this paper, we propose an FPGA slice design based on CNFET technology, and compare the performance and the power consumption characteristics of the proposed design with the same design based on Si-MOSFET. From the performance evaluation, we learned that the proposed design showed up to 5000 times better power-delay product (PDP) than the Si-MOSFET design. Especially reduction in power consumption was truly significant.

: A digital library taking advantage of the subthreshold mode of operation is studied and different gate topologies are explored for trade-offs in area, power, and propagation delay. Lowering the supply voltage allows for significant reductions in power consumption due to the squared dependence on voltage in switching logic. Dynamic-threshold metal-oxide semiconductor (DTMOS) inverters were used to improve the speed of inverters and buffers. Transmission gate logic was used to implement arbitrary logic gates to avoid PUN/PDN imbalances of static logic gates in subthreshold. These modifications result in the added benefit of smaller and simpler implementation of XOR/XNOR, making for a more modular nature to implement the common logic gates. The library is used to implement 1-bit full adders and a CIC filter with low power consumption.

This paper presents a new programmable frequency divider designed to generate any integer division of a parent clock frequency. We first introduce a new mathematical expression for the desired output clock period, which forms the basis of our proposed VLSI architecture. This architecture, primarily comprising two parallel comparators and counters, is inherently area-efficient and accurately handles the fractional component of frequency division. The proposed VLSI architecture has been successfully prototyped on a Basys-3 Field Programmable Gate Array (FPGA) board. Measured results demonstrate that the design generates output clock frequencies with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{5 0 \%}$</tex> duty cycle for even division ratios and a duty cycle between 40 % and 50 % for odd division ratios. The FPGA implementation utilizes 88 LUTs and 59 slice registers, achieving a maximum operating frequency of 118.23 MHz. Furthermore, the suggested VLSI architecture has been Application Specific Integrated Circuit (ASIC) synthesized and post-layout simulated in a 40 nm CMOS process. This ASIC implementation resulted in a compact core area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1103 \mu ~\mathrm{m}^{2}$</tex>. The design consumes 0.839 mW of power while operating at its maximum clock frequency of 1 GHz. A comparison with state-of-the-art implementations reveals that our proposed design achieves an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{8 9. 4 3 \%}$</tex> reduction in area and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{3 2. 7 7 \%}$</tex> reduction in power consumption.

Deep packet inspection (DPI) technology has conventionally been introduced for traffic monitoring, bandwidth control, bandwidth allocation, access control of specific types of traffic, etc. By installing a DPI equipment at any arbitrary point in a network, it is possible to monitor communications of many servers simply and this could simplify dramatically the conventional work load for system management and reduction of power consumption by servers. As a new potential application of DPI technology, this paper explores the possibility of applying DPI technology to server congestion control and reduction of power consumption by servers, and presents implementation examples of these applications. This paper first proposes an example of server congestion control method, in which the DPI equipment estimates the CPU usage of each server by constantly monitoring the number of live TCP connections established by each server, and moves some of virtual machines on the congested server to other servers through remote control timely. Next, this paper proposes an example of reducing power consumption by servers, in which the DPI equipment constantly monitors the traffic sent or received in each area with multiple servers. Finally, the feasibility of the proposed methods is demonstrated by an evaluation system with a real DPI equipment.

Objectives: Processors are computing elements of most of the embedded systems. As the technology is growing day by day, processors that are released in the market are mostly embedded processors. Processors are designed to perform concurrent operations and execution at a higher clock rate to meet the performance demands result in large heat dissipation and energy consumption. Thus there is an emphasis on power and energy consumption reduction in real time embedded processors. This work targets to reduce the processor power consumption without violating the real time constraints. Method: In this work, a dynamic power management technique named dynamic counters is employed in real-time system to minimize power consumption. The proposed method facilitates bounding of the events conservatively for effective bounding of future workload. It also employs scheduling ON and OFF time of the devices based on workload bounding at run-time. Simulation analysis is carried out to confirm the performance enhancement of the proposed method. Findings: Energy consumed by the processor increases with the number of event arrivals and switching of modes facilitates significant energy savings. Improvement: Run-time and memory overheads are overcome by dynamic counter technique. Effective bounding of future workload enhances computational efficiency.

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35µm CMOS process. It consumes 5.8mW at 100MHz with a single 3.3V power supply.

With the booming of artificial intelligence, convolutional neural networks (CNNs) have attracted widespread attention. In this paper, a look-up table (LUT) based multiplier array is proposed for convolution in CNNs, where multiplications play the critical role. By exploring the distinctive features of CNNs based on systolic array, the proposed multiplier array pre-computes all possible partial products and stores them in an LUT. The partial products in the LUT are reused multiple times to reduce the switching activities. The proposed multiplier array is employed in a multiply-and-accumulate (MAC) array for convolutional calculations. Implemented with different bit widths and clock frequencies in an industrial 65-nm CMOS technology, the proposed design achieves up to 23.34% and 33.26% reduction in power consumption as well as power area product (PAP), respectively, as compared to the reference designs with various conventional multipliers.

The standard cell power consumption reduction is one of primary goals of integrated circuit design, as the consumed power of chip has direct impact on chip lifetime and performance. There are different techniques of power consumption including power gating, low power design, voltage scaling, etc. The proposed method is aiming to power consumption reduction by standard cell sleep mode control using neural network integration. Presented enhancement methods of standard cells is inserting special addition in cells, hence giving opportunity to run the cell in sleep mode without consumpting power. Experiments show, that by using proposed method, power consumption is reduced by about 12% percent, while having increase in area by 5…28% and timing degradation by about ∼16%.

In this article, six structures/combinations of vertical-channel-FETs (VFETs) were optimized and performance comparison with lateral-gate-all-around (LGAA) FETs and complementary FET (CFET) was made in the advanced applications across device and circuit levels. To find the main resistive and capacitive parasitic, we introduce a novel decomposition methodology for classifying key gate capacitance components. Building on these insights, we propose two optimization strategies: an inner-spacer release technique for overlap capacitance reduction in VFETs and an additional trim-etch method to mitigate resistances. The optimal gate length is also discussed considering the unique channel arrangement of VFETs. Furthermore, we presented a standard cell layout for VFETs, which was used to make direct comparisons of performance–power–area (PPA) with lateral-channel-FETs (LFETs) for 103-ring oscillator (103RO) configurations. Compared to CFET, our simulation results demonstrate that dual-channel complementary stacked VFET (dCVFET) can increase the frequency by 4.4% in iso-power and decrease power by 12.9% in iso-frequency while reducing the area by 4.1%. Compared to LGAA, dual-channel single-layer VFET (dSLVFET) achieves a 14% speed improvement or a 30.7% reduction in power consumption while also reducing the area by 20%. When adopting wrap around contact (WAC), VFETs normally outperform LFETs by achieving nearly a 16% improvement in speed or a 40% reduction in power consumption under the same area.

In this study, we consider the problem of synthesising custom networks-on-chip (NoC) architectures that are optimised for a given application. Both unicast and multicast traffic flows are considered in the input specification. We formulate the joint multicast routing and network design problem using a rip-up and reroute procedure, where each multicast routing step is formulated as a minimum directed spanning tree problem, and we propose a very efficient algorithm called Ripup-Reroute-and-Router-Merging (RRRM). Our new formulation adopts a rip-up and reroute concept that provides us with a heuristic iterative mechanism to identify increasingly improving solutions. The minimum directed spanning tree formulation efficiently captures the best routing solutions for multicast flows during the topology synthesis procedure. Our design flow integrates floorplanning, and our solutions consider deadlock-free routing. Experimental results compared with our previous proposed algorithms CLUSTER and DECOMPOSE on a variety of NoC benchmarks showed that our new synthesis results are largely improved. RRRM can on average achieve a 9% reduction in power consumption over CLUSTER and a 17% reduction in power consumption over DECOMPOSE with 1786× and 57× faster execution times than CLUSTER and DECOMPOSE, respectively. Improvements in performance were also achieved, with an average of 3% reduction in hop counts over CLUSTER and 7% in hop counts over DECOMPOSE on all benchmarks.

Most modern digital receivers sample the received RF signal at an intermediate frequency (IF), then downconvert to the baseband in the digital domain. The baseband samples are subsequently correlated with a time-limited square pulse, which is readily implemented as an integrator. Since correlation is performed at the sampling frequency, the receiver correlates at an unnecessarily high frequency. This high frequency results in significant power dissipation especially if parallel correlators are employed. By downsampling after appropriate filtering to slightly above the signal Nyquist rate, correlation is achieved at a fraction of the sampling frequency, resulting in corresponding reduction in power consumption. Furthermore, by resampling to an integer number of samples per chip, architectural changes in the correlators are possible, allowing even more reduction in power consumption. In this paper, a resampling correlator with minimal hardware overhead that outperforms the conventional correlator is presented.

Design of unbalanced ternary counters using shifting literals based D-Flip-Flops in carbon nanotube technology