Standard Cell Library Enhancement Using Neural Network Based Sleep Mode Control Integration For Low Leakage Designs

Reducing the power consumption while maintaining the response time constraint has been an important goal in server system design. One of the techniques widely explored in the literature to achieve this goal is Dynamic Voltage Scaling (DVS). However, DVS is not efficient in modern systems where the overall power consumption includes a large portion of static power consumption. In this paper, we aim to reduce the static power consumption by Dynamic Power Management (DPM) with sleep model in addition to DVS. We propose a smart PowerSleep power-saving scheme, where a procrastination technique is adopted to carefully aggregate jobs to reduce the overhead of transitions in and out of the sleep mode. We also observe that PowerSleep might not always be a good choice due to the mode transition overhead when the server utilization is high, where instead we use PowerIdle power-saving scheme with DVS only. By modeling the system with M/G/1/PS queuing model and further extensions, we present how to minimize the mean power consumption of the server under the given mean response time constraint for both power-saving schemes. Simulation results show that our smart PowerSleep scheme significantly outperforms the simple power saving scheme which adopts sleep mode.

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

The drive for ultra efficient and low-cost portable devices continues to push the need for low power circuit designs. The increasing transistor density and complexity of IC designs aggravates the task of producing efficient low power and low cost design. The short time to market (TTM) also increases this burden on designers, as optimal designs have to be produced in an ever decreasing amount of time. This paper presents an optimization design flow methodology that optimizes the power (accounting leakage) consumption of integrated circuits (ICs). The design flow incorporates a stochastic gradient descent (SGD) based algorithm and is implemented using a 45 nm thermal sensor circuit as case study. Power-efficient high-sensitive thermal sensors are important to reduce the burden on the systems or circuits that they are implanted to sense. Experiments are performed to apply the proposed design flow methodology on the thermal sensor with the power consumption as the design objective while keeping the temperature resolution as a constraint. Experiments on full-blown (RCLK) netlist of sense amplifier show a reduction in power consumption by 38%.

Metal Oxide Thin Film Transistors (MO TFTs) have garnered considerable interest in emerging Internet of Things (IoT) fields such as wearable electronics, displays, Radio Frequency Identification (RFID), and biomedical monitoring, owing to their flexibility and transparency. However, limitations in channel materials make MO TFT-based circuits unipolar. Unipolar circuits often exhibit elevated short-circuit power consumption, which restricts the development of MO TFTs in the IoT sector. This paper introduces a Capacitively Coupled Near-Threshold Biasing (CCNB) technique that leverages the unique Capacitance-Voltage (C-V) characteristics of MO TFTs to bias devices in the near-threshold region, achieving nearly a 95% reduction in power consumption compared to traditional designs with the device coupling ratio (channel capacitance/overlap capacitance) at 40. Furthermore, considering the significance of clock signals in IoT applications, we have also developed a low-power full-swing Ring Oscillator (RO) based on our CCNB technique, resulting in a 90% reduction in power consumption and a nearly 70% reduction in PDP compared to conventional low-power designs.

Reduction of the size and the power consumption of the DFF, the component that has the largest area occupancy in the standard cell, is extremely useful for the reduction of the same characteristics in the entire chip. The proposed DFF is a semistatic configuration realizing True-Single-Phrase Clocking (TSPC). In comparison with the conventional circuit, this one is successful in reduction of power consumption and in improvement of circuit characteristics such as noise endurance. Also, even though the number of NMOSs is almost twice that of PMOSs, the lateral pitch is less than in the conventional small DFFs fabricated with the 0.25-μm SIMOX, bulk, and MT-CMOS low threshold process common layout, by virtue of a layout in which only the NMOSs are multistaged. The standard cell blocks designed with the proposed DFF are fabricated by a 0.25-μm SIMOX process. The power consumption is computed by measurement of the supply current. It is found that the power consumption is reduced by 23% on average in comparison with circuits using the conventional DFF. © 1999 Scripta Technica, Electron Comm Jpn Pt 2, 82(3): 22–30, 1999

Due to limited battery power that devices have, an efficient DVFS (Dynamic Voltage and Frequency Scaling) algorithm is important. DVFS applies not only to the CPU, also the shared cache and memory associated with the CPU. The CPU and these memory hierarchy interact with each other, however, their DVFS methods are operated independently. Although there have been many discussions to reduce the memory access latency of CPU, the conventional DVFS technique does not relieve memory stall (the state during which CPU is stalled waiting for a memory access) effectively due to individual DVFS methods. In this article, we propose a new DVFS method, which alleviates the memory stall and reduces CPU power consumption utilizing microarchitectural information. Our proposed method identifies the layer on the memory hierarchy that mainly generates the memory stall and determines the optimal frequency of CPU and memory hierarchy that achieve a system-wide power optimization, without degrading the performance. In our experiments, our proposed method improved IPC (Instruction Per Cycle) by 11%, reduced MSPC (Memory Stall Per Cycle) by 26% and reduced power consumption by 5% compared to a conventional DVFS method.

Objectives: Processors are computing elements of most of the embedded systems. As the technology is growing day by day, processors that are released in the market are mostly embedded processors. Processors are designed to perform concurrent operations and execution at a higher clock rate to meet the performance demands result in large heat dissipation and energy consumption. Thus there is an emphasis on power and energy consumption reduction in real time embedded processors. This work targets to reduce the processor power consumption without violating the real time constraints. Method: In this work, a dynamic power management technique named dynamic counters is employed in real-time system to minimize power consumption. The proposed method facilitates bounding of the events conservatively for effective bounding of future workload. It also employs scheduling ON and OFF time of the devices based on workload bounding at run-time. Simulation analysis is carried out to confirm the performance enhancement of the proposed method. Findings: Energy consumed by the processor increases with the number of event arrivals and switching of modes facilitates significant energy savings. Improvement: Run-time and memory overheads are overcome by dynamic counter technique. Effective bounding of future workload enhances computational efficiency.

Cyber Physical Systems are composed of many embedded systems which monitor and control the physical processes for tight integrations of computation and physical processes. Such embedded systems require not only real-time capabilities but also high throughput and low power consumption. High throughput is mainly achieved by parallel architectures such as Simultaneous Multithreading (SMT) and Chip Multiprocessor (CMP), and low power consumption is mainly achieved by Real-Time Dynamic Voltage and Frequency Scaling (RT-DVFS) under the real-time constraint. In this paper, we present a RT-DVFS algorithm called Hetero Efficiency to Logical Processor (HeLP) which can reduce power consumption easily and effectively in prioritized SMT processors. We also present Hetero Efficiency to Logical Processor with Temporal Migration (HeLP-TM) which applies the temporal migration technique to HeLP. Simulation results show that HeLP can reduce power consumption effectively and HeLPTM is more effective than HeLP.

Both the capacity and the complexity of modern FPGA devices increase rapidly. Also, it is common that battery-powered embedded systems are equipped with FPGA devices. Therefore, reducing the power consumption of FPGA devices has become a very crucial issue. Not only dynamic power consumption but also leakage power consumption increases as the feature size to manufacture FPGA devices shrinks. To reduce the power consumption of FPGA devices, carbon-nanotube field effect transistor (CNFET) has emerged as a promising candidate for replacing silicon metal oxide semiconductor field effect transistor (Si-MOSFET). In this paper, we propose an FPGA slice design based on CNFET technology, and compare the performance and the power consumption characteristics of the proposed design with the same design based on Si-MOSFET. From the performance evaluation, we learned that the proposed design showed up to 5000 times better power-delay product (PDP) than the Si-MOSFET design. Especially reduction in power consumption was truly significant.

Shrinking feature sizes, reduced voltages, and higher transistor count of nano-scale silicon chips challenge designers in terms of performance, power consumption, and reliability. This paper investigates the effect of simultaneous use of dynamic voltage and frequency scaling (DVFS) and body biasing (BB) on power consumption, reliability, and performance. An analytical model of reliability as a function of body bias voltage, supply voltage, and frequency is proposed. We derive a three dimensional optimization problem by exploiting proposed reliability model in conjunction with power consumption and performance model. The resulting problem is solved using widely-used geometric optimization to identify optimal supply voltage and body bias voltage and then is validated using accurate simulation. Afterwards, it is demonstrated how joint energy-performance-reliability space optimization method can be used in an adaptive reliability-aware power management systems. Finally, we show that combined soft error aware BB and DVFS is capable of improving power consumption about 30% in comparison to reliability-aware DVFS only for the same level of reliability and performance constraints.

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35µm CMOS process. It consumes 5.8mW at 100MHz with a single 3.3V power supply.

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

Increasing speed and complexity of design gives a significant increase in power consumption in VLSI chips. Speed, power consumption and space are major issues in VLSI circuit. To meet these challenges there are certain design techniques which are used to reduce power. Optimization of power can be done by considering various components such as transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, power gating, long channel transistor, stacking & parking states and logic styles etc. Power consumption in VLSI circuit is data dependent. In this paper different design methods are tested to optimize the power. It is found that algorithm based design reduces gate switching activity that results reduction of power in multiplier circuit. Keyword: Transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking & parking states, logic styles, Genetic algorithm, Booth multiplication I. Introduction Reduction in power dissipation is an important design issue in VLSI circuits. The design parameters have major effect on the overall performance of the system. On the basis of component used and their function different optimization techniques can be used. For example in case of multiplier power consumption depends upon data. This is because switching contributes to more power consumption. This can be optimized by using various gate combinations. Gate switching can be reduced by using algoritms. For example of in case of multiplier design method Booth algorithm as well as modified Booth algorithm can be used for efficient multiplication. In this paper various approaches are used for power consumption eg. transistor sizing, voltage scaling, variable VDD, multiple threshold voltages, voltage islands, long channel transistor, stacking& parking states, logic styles, Genetic algorithm, Booth multiplication etc. This paper is divided into five sections. First section is of introduction. Second section is about preliminary studies. Third section includes different design methods and their testing. Fourth section is of comparison with discussion. Finally, fifth section is conclusion of the work reported here.

In this paper, we propose a novel dynamic point selection (DPS) and user scheduling method for improving the energy efficiency in distributed antenna systems without cell edge spectral efficiency degradation. When DPS is used, each user is served by a single transmission point that can be dynamically switched. The proposed method decreases the power consumption by switching off inactive radio frequency (RF) chains and additionally reduces the interference by a static inter-cell agreement on which transmission points are simultaneously active. The performance of the method is evaluated by computer simulations in a system that accurately models the LTE-Advanced (LTE-A) intra-cell coordinated multi-point scenario 4. Based on the performance simulations, the proposed method achieves a significant energy efficiency gain over closed-loop spatial multiplexing applied on localized or distributed transmitting antennas. In general, the proposed method performs well when the load-independent RF power consumption is high in the active mode and low in the sleep mode. When the proportion of the load-independent RF power consumption to the total load-independent power consumption exceeds a certain limit, which is 22 % in the case of ten users in the 3-sector layout, the proposed method brings always energy efficiency gain even when RF chain micro sleeping cannot be implemented. The usability of the method is not dependent on the traffic load. The same approach can be applied to any distributed antenna system.

The multiplier is the most basic unit of an arithmetic circuit which is predominantly used in digital processing units and several integrated circuits. The efficiency of a processing unit is measured by its speed and power consumption. The multiplier circuit involves an extensive use of adders that generally add to its hardware complexity and thus is a major bottleneck to fast processing and also consumes high power. Thus it becomes critical to improve speed and reduce power consumption in the multiplier module. The conventional multipliers implemented using the CMOS and GDI technologies and their combination versions, albeit showing improved speed and low power consumption, still suffer from high hardware complexity. This paper proposes the design of an 8-bit hybrid Wallace tree multiplier. The key idea here is to use the power efficient GDI technology based 1-bit hybrid full adder within the popularly used array and Wallace tree multipliers to obtain a new multiplier design with fewer transistors and full output voltage swing. The proposed designs are implemented using Tanner EDA with 250nm technology and simulation results show substantial improvement when compared with the state-of-the- art.