<title>Media processors using a new microsystem architecture designed for the Internet era</title>

Most artificial neural networks are designed using an analog model derived from the McCulloch-Pitts neuron model. This design is then implemented as a simulation on a digital computer, and few designs are implemented in dedicated analog hardware. Many simulations run at a small fraction of the speed that analog hardware would allow, but custom designed analog circuitry is usually too expensive. In this paper I will introduce a digital neuron model for artificial neural networks. The purpose of this model is to simplify the design of digital neural networks and allow the design of custom hardware using common digital parts. >

The new demands for high-definition and high resolution video applications are pushing the development of new techniques in the video coding area. Motion estimation (ME) is one of the key elements in video coding standard which eliminates the temporal redundancies between successive frames. In the recent international video coding standards, sub-pixel ME is proposed for its excellent coding performance. DCT (Discrete Cosine Transform) has been widely used for digital signal processing and multimedia applications, especially video codec. In regards to interpolation for motion estimation and compensation, the conventional HEVC employs 8-tap and 4-tap filters for luma and chroma samples respectively. Coefficients in such filters are determined by DCT. This paper presents and implements the DCT-based Quarter-pixel Interpolation filter for motion estimation and compression of HEVC standard using Matlab.

Android is an open-source project used for mobile devices and embedded system applications. It is a customizable and optimizable operating system, which are two important features for the design and implementation of specific tasks applications. Android originally comes with a lot of running services and apps in the background supporting a lot of features and device peripherals. All of these extra features and components reduce the performance of the specific task application. Also, the size of the system will be much higher than expected and need large memory footprint. The custom hardware design is out of our work scope. The aim of our work is to use the already implemented board designed by Samsung called "Klte" to implement an android-based multimedia application called "Car Audio Player". In our work, we focus on the customization and optimization tasks to make the Android works efficiently and reliably with our application. Therefore, we deal with the Android Kernel source code by disabling all unneeded modules and optimizing the boot time by choosing faster kernel decompress algorithm. Then, the source code will be built to generate the new system image which is more efficient and reliable for our specific application. Because every Android operating system needs a tool that help the technical user to carry out control and maintenance for the system in case of damage or urgent change, we design an administration tool specifically for our application. These tool gives the technical admin many control and maintenance commands to support the operating system without the need to return to the designer in urgent situations.

High-level synthesis (HLS) is the automatic compilation of software programs into custom hardware designs. With programmable hardware devices (such as FPGAs) now widespread, HLS is increasingly relied upon, but existing HLS tools are too unreliable for safety- and security-critical applications. Herklotz et al. partially addressed this concern by building Vericert, a prototype HLS tool that is proven correct in Coq (à la CompCert), but it cannot compete performance-wise with unverified tools. This paper reports on our efforts to close this performance gap, thus obtaining the first practical verified HLS tool. We achieve this by implementing a flexible operation scheduler based on hyperblocks (basic blocks of predicated instructions) that supports operation chaining (packing dependent operations into a single clock cycle). Correctness is proven via translation validation: each schedule is checked using a Coq-verified validator that uses a SAT solver to reason about predicates. Avoiding exponential blow-up in this validation process is a key challenge, which we address by using final-state predicates and value summaries. Experiments on the PolyBench/C suite indicate that scheduling makes Vericert-generated hardware 2.1× faster, thus bringing Vericert into competition with a state-of-the-art open-source HLS tool when a similar set of optimisations is enabled.

The maximum matching algorithm for bipartite graphs can be used to provide optimal scheduling for crossbar based interconnection networks. Unfortunately, maximum matching requires O(N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ) time for an N times N communication system, which has limited its application to real-time network scheduling. In this paper, we show how maximum matching can be reformulated in terms of Boolean operations rather than the more traditional formulations. By taking advantage of the inherent parallelism available in custom hardware design, we introduce three maximum matching implementations in hardware and show how we can trade design complexity for performance. Specifically, we examine a pure logic scheduler with three dimensions of parallelism, a matrix scheduler with two dimensions of parallelism and a vector scheduler with one dimension of parallelism. These designs reduce the algorithmic time complexity down to O(1), O(K), and O(KN), respectively, where K is the number of optimization steps. While an optimal scheduling algorithm requires K=2N-1 steps, our simulation results show that the scheduler can achieve 99% of the optimal schedule when K=9. We examine hardware and time complexity of these architectures for crossbar sizes of up to N=1024. Using FPGA synthesis results, we show that a greedy schedule for various sized crossbars, ranging from 8 times 8 to 256 times 256, can be optimized in less than 20 ns per optimization step. For crossbars reaching 1024 times 1024 the scheduling can be completed in approximately 10 s with current technology and could reach under 90 ns with future technologies

We present a strategy for block-based motion estimation that involves transforming video sequences from a multibit to a one-bit/pixel representation, and then applying conventional motion estimation search strategies. This results in substantial reductions in arithmetic and hardware complexity, and reduced power consumption, while maintaining good compression performance. Experimental results and a custom hardware design are also presented.

The maximum matching algorithm for bipartite graphs can be used to provide optimal scheduling for crossbar based interconnection networks. Unfortunately, maximum matching requires O(N3) time for an N x N communication system, which has limited its application to real-time network scheduling. In this paper, we show how maximum matching can be reformulated in terms of Boolean operations rather than the more traditional formulations. By taking advantage of the inherent parallelism available in custom hardware design, we introduce three Maximum Matching implementations in hardware and show how we can trade design complexity for performance. Specifically, we examine a Pure Logic Scheduler with three dimensions of parallelism, a Matrix Scheduler with two dimensions of parallelism and a Vector Scheduler with one dimension of parallelism. These designs reduce the algorithmic time complexity down to O(1), O(K), and O(KN), respectively, where K is the number of optimization steps. While an optimal scheduling algorithm requires K = 2N -- 1 steps, our simulation results show that the scheduler can achieve 99% of the optimal schedule when K = 9. We examine hardware and time complexity of these architectures for crossbar sizes of up to N = 1024. Using FPGA synthesis results, we show that a greedy schedule for various sized crossbars, ranging from 8 x 8 to 256 x 256, can be optimized in less than 20 ns per optimization step. For crossbars reaching 1024 x 1024 the scheduling can be completed in approximately 10 μs with current technology and could reach under 90 ns with future technologies.

This paper presents pipeline vectorization, a method for synthesizing hardware pipelines based on software vectorizing compilers. The method improves efficiency and ease of development of hardware designs, particularly for users with little electronics design experience. We propose several loop transformations to customize pipelines to meet hardware resource constraints while maximizing available parallelism. For runtime reconfigurable systems, we apply hardware specialization to increase circuit utilization. Our approach is especially effective for highly repetitive computations in digital signal processor (DSP) and multimedia applications. Case studies using field programmable gate arrays (FPGAs)-based platforms are presented to demonstrate the benefits of our approach and to evaluate tradeoffs between alternative implementations. For instance, the loop-tiling transformation, has been found to improve vectorization performance 30-40 times above a PC-based software implementation, depending on whether runtime reconfiguration (RTR) is used.

The recent years have witnessed a variety of new embedded applications. Typical examples include mobile multimedia gadgets, digital televisions, high-end cell phones, wireless network applications, etc. The salient features of these applications include more comprehensive functionalities, higher performance demand, and low-power consumption. These requirements render the traditional single processor-based embedded systems no longer an appropriate realization for such applications. On the other hand, the continual advance of VLSI technologies enables more and more transistors to be integrated on a single chip. The International Technology Roadmap for Semiconductors predicts that chips with a billion transistors are within reach. As a result, the push (application demands) and pull (VLSI technology) forces together give birth to the multi-processor system-on-chips (MPSoCs).Heterogeneous MPSoCs are different from traditional embedded systems in many aspects and they ask for new design and implementation methodologies. Heterogeneous MPSoCs are not merely a hardware design. The complexity and heterogeneity of the system significantly increase the complexity of the HW/SW partitioning problem. Meanwhile, evaluating the performance and verifying its correctness is much more difficult compared to traditional single processor-based embedded systems. Constructing a simulator to simulate the system’s behavior and evaluate its performance takes more effort compared to conventional embedded systems. The verification of the system also becomes challenging.Programming a heterogeneous MPSoC is another challenge to be faced. This problem arises simply because there are multiple programmable processing elements and since they are heterogeneous, software designer needs to have expertise on all of these processing elements and needs to take a lot of care on how to make the software running as a whole.There are a lot more issues that do not appear or easier to tackle on traditional embedded systems, trade-offs between performance and low-power will dominate the design life time. However, the incoming challenges also brought us many opportunities either to industry and academic research.

The objective of the present study is to investigate the capability of field-programmable gate array hardware in numerical simulation of a model of a dielectric barrier discharge plasma actuator to accelerate the calculations. The reconfigurable hardware is designed such that it is possible to reprogram its architecture after manufacturing. This provides the capability to design and implement various architectures for several applications. Two reconfigurable chips are used in the present study, one of which consists of a programmable logic unit and a typical microprocessor. This hybrid architecture makes the high performance of the reconfigurable hardware in custom computing and the efficiency of the microprocessor in data flow control accessible. An automated design procedure is used for the design of the reconfigurable hardware. Further, a finite difference representation of a phenomenological model of a plasma actuator is derived and implemented on the field-programmable gate array hardware. The results are validated against other numerical data, and the computational time is compared to different conventional processors. Using the reconfigurable hardware results in up to 96% computational time reduction compared to a recent Core i7 processor.

Designing efficient, application-specialized hardware accelerators requires assessing trade-offs between a hardware module’s performance and resource requirements. To facilitate hardware design space exploration, we describe Aetherling, a system for automatically compiling data-parallel programs into statically scheduled, streaming hardware circuits. Aetherling contributes a space- and time-aware intermediate language featuring data-parallel operators that represent parallel or sequential hardware modules, and sequence data types that encode a module’s throughput by specifying when sequence elements are produced or consumed. As a result, well-typed operator composition in the space-time language corresponds to connecting hardware modules via statically scheduled, streaming interfaces. We provide rules for transforming programs written in a standard data-parallel language (that carries no information about hardware implementation) into equivalent space-time language programs. We then provide a scheduling algorithm that searches over the space of transformations to quickly generate area-efficient hardware designs that achieve a programmer-specified throughput. Using benchmarks from the image processing domain, we demonstrate that Aetherling enables rapid exploration of hardware designs with different throughput and area characteristics, and yields results that require 1.8-7.9× fewer FPGA slices than those of prior hardware generation systems.

This book consists of 35 chapters presenting different theoretical and practical aspects of Intelligent Information and Database Systems. Nowadays both Intelligent and Database Systems are applied in most of the areas of human activities which necessitates further research in these areas. In this book various interesting issues related to the intelligent information models and methods as well as their advanced applications, database systems applications, data models and their analysis and digital multimedia methods and applications are presented and discussed both from the practical and theoretical points of view. The book is organized in four parts devoted to intelligent systems models and methods, intelligent systems advanced applications, database systems methods and applications and multimedia systems methods and applications. The book will be interesting forpractitioners and researchers, especially graduate and PhD students of information technology and computer science, as well more experienced academics and specialists interested in developing and verification of intelligent information, database and multimedia systems models, methods and applications. The readers of this volume are enabled to find many inspiring ideas and motivating practical examples that will help them in the current and future work.

This brief introduces a low-cost hardware design for approximate squaring functions which preserve maximum information content of the signals in template-matching applications. Analysis of signal statistics for two example applications, i.e., motion estimation and disparity estimation, is presented. This information is then specifically incorporated in the hardware design process to develop approximate squarers which outperform existing designs in hardware resource savings and performance while processing real-world data. Specifically, the proposed architectures make distinction between low- and high-entropy portions of the input data to intelligently trade off bit precision with hardware complexity. Mathematical and experimental results show mean-relative-error figures to be as low as 1.2% and the performance to be as good as conventional full-precision processing scenarios. Implementation results for current-generation six-input look up table (LUT) and four-input LUT FPGAs have been discussed in relation to the proposed design flow.

While acousto-optic bulk or surface wave devices represent a radical change in system architecture to overcome the throughput limitations of conventional signal processor technology, GaAs IC's use the conven-tional digital or analog semiconductor processor architectures, achieving greatly improved throughputs by implementing these devices with a radically improved semiconductor. The superior electronic properties of GaAs, as compared with silicon, make possible the achievement of much higher performance levels in GaAs signal processing devices than have been demonstrated with silicon. Only recently, however, have advances in GaAs materials and processing technology made possible the fabrication of such devices as sub1100 ps propagation delay, high density planar GaAs integrated circuits with LS compatible power levels, and high speed (>0.5 GHz), high transfer efficiency GaAs charge coupled devices, 5 which should be capable of multi-gigahertz clocking rate operation. These high performance device technologies should have major impact on the high speed signal processing area, making possible, through their much higher speeds and lower power requirements, system approaches which could not be practically realized with existing silicon technology.© (1980) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Adaptive antenna applications demand high-performance, control and data intensive processing, and are deployed in energy constrained envi-ronments. Heterogeneous embedded systems that integrate several components such as reconfigurable devices, general purpose processors or DSPs, and memory onto a single system are attractive targets for implementing such applications. Such systems support various capabilities such as reconfiguration, dynamic voltage and frequency scaling, and low-power operating states. Such choices during application design result in a large design space that must be traversed efficiently. We propose an embedded system design environment that enables efficient traversal of a large design space. The environment supports modeling of adaptive antenna applications, candidate hardware architectures, mapping information, performance requirements, and design constraints. Using the information captured in the models, the environment facilitates rapid design space exploration using optimization heuristics and hierarchical simulation. The design environment can be used to identify energy and latency efficient mappings for a given application and target hardware, or, if a set of hardware choices are given, select the most energy efficient hardware and the corresponding mapping. We illustrate the advantages of the design environment through efficient hardware selection for, and mapping of, an adaptive minimum variance distortionless response beamformer.KeywordsDesign SpaceSmart AntennaDesign Space ExplorationDynamic Voltage ScalingAutomate Target RecognitionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.