Monolithically Integrated Vertical Monolayer MoS2 Field-Effect Transistors Via Direct-Growth
Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as a first-rate candidate for post-silicon channels in field-effect transistors (FETs), particularly in the context of monolithic three-dimensional (M3D) integration. Despite the recent synthetic advances including industry-compatible wafer-scale production, they have predominantly been prepared on the ultra-flat, non-processed surfaces, limiting device architectures to outdated planar FETs and geometrically restricting their versatile applications. Integrating 2D semiconductors into 3D device architectures currently presents two significant challenges: i) stackablity, and ii) scalablility. While 2D material-based FETs have been primarily limited to traditional planar devices structures, their applications to vertically integrated 3D devices have been hindered by low-fidelity transfer method which is certainly challenging in conformally and controllably transferring atomically thin materials onto steep sidewalls. Here, we report a directly growth-and-fabrication approach enabling the dimensional transition from 2D planar FETs to a 3D vertical-channel FETs (VCFETs) through the atomically conformal direct growth of monolayer (ML) MoS2 onto the pre-fabricated VCFET structures (Fig. 1A). Leveraging the inherently anisotropic in-plane growth kinetics and precisely controlled supersaturation based on metal-organic chemical vapor deposition, we achieved 100% step coverage even with sub-1-nm channel thickness without compromised crystallinity along an exceptionally high aspect ratio exceeding 15,000 (Fig. 1B). We proved that monolayer MoS2 grown along the SiO2 vertical sidewall is a single crystal by comparing the angles of the selected-area electron diffraction (SAED) pattern in transmission electron microscope (TEM) at the three vertices of MoS2 (Fig. 1C). Fig. 1D shows a cross-sectional scanning transmission electron microscope (STEM) image of the VCFET with and spatial distribution of each element was also identified by energy dispersive X-ray spectroscopy (EDS) mapping images, and it convincingly suggests that atomically conformal monolayer MoS2 was indeed integrated without discontinuity and void even along a steep trench edge (Fig. 1D). Fig. 1E illustrates the unit device schematic of the monolayer MoS2 VCFET. The experimental and simulated transfer characteristic (I DS-V GS) of VCFET with vertical monolayer MoS2 well-coincide each other, showing the subthreshold swing (SS) of 77mV·dec−1 and the ON/OFF ratio of 108 under a drain-to-source bias (V DS) of 1V (Fig. 1F). Output characteristic (I DS-V DS) indicates the change in conductivity of the MoS2 channel by regulating the V G at steps of 1V from −2V to 5V (Fig. 1G). To evaluate device-to-device variation and statistic distribution of their performance, electrical characterization of the 7×7 VCFETs array was performed and their I DS-V GS curves under V DS = +1V exhibited the excellent reproducibility (Fig. 1H). Fig. 1I shows low OFF-state current density of 10−13A∙μm−1 at all devices in our monolayer MoS2 VCFET array, which is 10 times lower than the International Roadmap for Devices and Systems (IRDS) 2028 low-standby power device requirement (~10−12A∙μm−1). Sentaurus technology computer-aided design (TCAD) simulations for monolayer MoS2 VCFET were performed to investigate the electric field distribution of ON-state (V GS = +5V) and OFF-state (V GS = −2V), respectively (Fig. 1J-K). To demonstrate how electron concentration changes in monolayer MoS2 at the sidewall control the switching operation of the transistor, we fabricated a multi-gate VCFET (Fig. 1L). The additional terminals, a modulation gate (MG) and a back gate (BG), facilitate to form an effective gate length near the control gate (CG), enabling a switching behavior of the transistor. The MG screens the electric field toward the top of the trench from the CG, maintaining the electron concentration of the monolayer MoS2 on the top region of the trench and restricting switching operation to monolayer MoS2 on the vertical sidewall. I DS-V CG curve was obtained by applying the CG bias (V CG) and the BG bias (V BG) of +30V with the floated MG bias (V MG) (Fig. 1M). The fabricated multi-gate VCFET further validated the superior sidewall-gate controllability of the ultrathin monolayer MoS2 channel on the vertical sidewall, with aid of TCAD simulation. In the ON-state (V CG = +2.5V), the MG screens electric field generated by CG, allowing the electric field of CG to accumulate electrons effectively along the vertical monolayer MoS2 sidewall, as shown in Fig. 1N. in the OFF-state (V CG = −2.5V), the electric field contour plot reveals that the electric field from the CG does not reach the top region of trench due the MG, while forming a strong electric field near the CG, leading to deplete the MoS2 channel (Fig. 1O). Our work establishes a tailored pathway for the bespoke monolithic integration of ML semiconductors, positioning them as viable channels for high-density, high-performance computational device. Our integration strategy is undisputed pathway for M3D integration and usher in a new era of atomic-level fabric. Figure 1
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