A Novel SiGe Nanosheet Transistor With Channel Release Stopping Layer Structure for Process Variations Suppression and Circuit Performance Improvement

In this paper, we carried out detailed technology computer aided design simulations to investigate the radiation effects, e.g. total ionizing dose (TID) and single-event effects (SEEs), on direct current (DC) and radio frequency (RF) characteristics of the gate-all-around (GAA) nanosheet field-effect transistor (FET). The simulation model used is composed of seven-layer stacked GAA nanosheet FET with L g = 22 nm, which was implemented in this study. The open current and the drain-induced barrier lowering of the device are ∼3 mA μm−1 and 47 mV V−1, respectively. The results indicate that the TID have little influence on the DC and RF characteristics when the transistor is working in an open state. During the SEEs simulation, we considered three incident directions for the high energy particle, including the lateral direction of the channels, the vertical direction of the channels and the top of the channels. The influence of the particle injecting along the lateral and vertical directions of the channels shows stronger relation with the distance from the incident point compared to the influence of the particle from the top. Besides, the general influence of the particle injecting along the lateral directions of the channels is higher than the other two directions. The total injected charge of the particle injecting along the lateral direction, along the vertical direction and from the top are 3 fC, 1.4 fC and 2.1 fC, respectively. As compared to the fin FET, the GAA nanosheet has superior RF performances and less sensitivity to TID effect. This work can provide a guideline for the GAA nanosheet devices in aerospace and avionic RF applications.

In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model.

Using three-dimensional technology computer-aided design (TCAD) simulation, parasitic bipolar amplification in a single event transient (SET) current of a single transistor and its temperature dependence are studied. We quantify the contributions of different current components in a SET current pulse, and it is found that the proportion of parasitic bipolar amplification in total collected charge is about 30% in both 130-nm and 90-nm technologies. The temperature dependence of parasitic bipolar amplification and the mechanism of the SET pulse are also investigated and quantified. The results show that the proportion of charge induced by parasitic bipolar increases with rising temperature, which illustrates that the parasitic bipolar amplification plays an important role in the charge collection of a single transistor.

In this study, we investigated the impact of random dopant fluctuation (RDF) on junctionless (JL) fin field-effect transistors (FinFETs) with ferroelectric (FE) negative capacitance (NC) effect. The RDF-induced variations were captured by using built-in Sano methodology in three-dimensional technology computer-aided design (TCAD) simulation. Compared to the regular JL-FinFETs, the variations in JL-FinFETs with NC effect (NCJL-FinFETs) was observed to be less via statistical Monte Carlo analysis, which further enhanced its performance as well. The evaluation and estimation of threshold voltage (V T ), ON-state current (I on ), OFF-state current (I off ), and subthreshold swing (SS) by different FE layer thicknesses indicated reduction in the standard deviations of V T (δV T ) and I on (δI on ) by 34.7% and 7.08%, respectively; the OFF-state current and its standard deviation shrank by approximately three orders of magnitude than the JL-FinFET counterpart. Although δSS was not monotonous, the SS was significantly improved to sub-60 mV/decade. To sum up, the regular JL-FinFETs containing the FE layer as NC effect not only improved the electrical performance, but also led to the resilience of the RDF-induced statistical variability.

The hump behavior of gate-normal nanowire tunnel field-effect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing (SS) and on-current (Ion) because the corners and sides of nanowires (NWs) have different surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature (R) of NWs and reducing gate insulator thickness (Tins).

We study the performance of vertically stacked InGaAs/InAlAs/InP Double Quantum Well (DQW) Fin Field Effect Transistor (FinFET) on Si substrate using three-dimensional Technology Computer-Aided Design (TCAD) simulation. In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As and In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.48</sub> As are used as the quantum well channel and the barrier material, respectively. Both materials are lattice matched to the InP buffer layer material on Si substrate. The device is simulated with gate lengths (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) of 15 nm and gate stack (Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) of 1nm/2nm (EOT~0.75nm). The simulation results reveal that by using double channel quantum well (super lattice structure) can enhance the saturation current up to 24% compared to Single Quantum Well (SQW) device. The maximum capacitance of the DQW also outperforms the SQW FinFET approximately 34%. The higher capacitance indicates the higher carrier density. The electron density of DQW prefers to localize in the InGaAs layer as the quantum well channel, thus allow greater control over the electron behavior. The device characteristics indicate that the DQW FinFET on Si substrate can be alternated to enhance the device performance for prospective high performance logic device applications.

The mainstream optimization scheme for parasitic capacitance using low-κ material for outer and inner spacers has drawbacks such as poor robust characteristics of materials and profile control of inner spacers, resulting in deterioration of driving performance of advanced gate-all-around (GAA) nanosheet field effect transistors (NSFETs). To overcome the problem of high parasitic capacitance in GAA NS devices, while reconciling the requirements for high-quality inner spacers and good driving performance, we propose a hybrid dual-κ spacer strategy, using low-κ material for outer spacers and more robust Si3N4 material for inner spacers. The proposed hybrid dual-κ spacer scheme not only solves the poor profile uniformity problem of inner spacers by using more Si3N4 at the inner spacer position but also optimizes the parasitic capacitance of the device by 14.51% (NMOS) and 11.70% (PMOS) than single SiNx spacers, while maintaining its driving characteristics (10.00% (NMOS) and 17.01% (PMOS) better than single low-κ spacers) simultaneously. Circuit performances are thereby improved by 108.41% for 17-stage ring oscillators output frequency and 20.14% for write time in an SRAM unit. Therefore, the proposed scheme is qualified to provide an ideal solution for high-quality production of GAA devices and high-performance circuit applications.

The radiation effects on a multi-nanosheet tunneling-based field effect transistor (NS-TFET) were investigated for a 3-nm technology node using a three-dimensional (3D) technology computer-aided design (TCAD) simulator. An alpha particle was injected into a field effect transistor (FET), which resulted in a drain current fluctuation and caused the integrated circuit to malfunction as the result of a soft-error-rate (SER) issue. It was subsequently observed that radiation effects on NS-TFET were completely different from a conventional drift-diffusion (DD)-based FET. Unlike a conventional DD-based FET, when an alpha particle enters the source and channel areas in the current scenario, a larger drain current fluctuation occurs due to a tunneling mechanism between the source and the channel, and this has a significant effect on the drain current. In addition, as the temperature increases, the radiation effect increases as a result of a decrease in silicon bandgap energy and a resultant increase in band-to-band generation. Finally, the radiation effect was analyzed according to the energy of the alpha particle. These results can provide a guideline by which to design a robust integrated circuit for radiation that is totally different from the conventional DD-FET approach.

The variations of single event transient (SET) pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor (FinFET) inverter chains with different driven strengths are measured at different temperatures. Three-dimensional (3D) technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature. Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk FinFET technology, resulting in the increase of SET pulse width. On the other hand, the increase of inverter driven strength will change the layout topology, which has a complex influence on the SET temperature effects of FinFET inverter chains. The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

&lt;p&gt;Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.&lt;/p&gt;

We propose a physics-based analytical model that accurately captures the effects of buffer traps on dc characteristics of gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs). The model is then semi-analytically extended to additionally include the transient behavior. Analytical formulations for the shift in the threshold voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${(}{V}_{\text {OFF}}{)}$ </tex-math></inline-formula> and two-dimensional electron gas (2-DEG) density due to the presence of buffer traps in the steady state are presented. In pulsed operation, technology computer-aided design (TCAD) simulations indicate that a time-dependent negative potential (NP) is developed under the gate, resulting in a modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {OFF}}$ </tex-math></inline-formula> and current collapse (CC). An expression for the modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {off}}$ </tex-math></inline-formula> helps capture the pulsed current–voltage characteristics. The model captures the dependence of bias, time, temperature, trap concentration, capture cross section area, and activation energy of traps on the steady-state and transient characteristics. The model is implemented in Verilog-A in an existing compact model framework using a diode and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> sub-circuit and validated using measured data and TCAD simulations. The modeling results are in excellent agreement with the experimental data and TCAD simulations. Since the model is physics-based, it requires fewer number of parameters compared to that in the existing models.

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.

Study of parasitic oscillation of a multi-chip SiC MOSFET circuit based on a signal flow graph model by TCAD simulation

This work evaluates the potential impact of interface traps on the interface of oxide and semiconductor on a 2-D-based ion-sensitive field-effect transistor (ISFET) using a surface potential-based model and Technology Computer-Aided Design (TCAD) simulation calibrated for pH sensing applications. The electrolyte/oxide interface in the proposed 2-D ISFET model is modeled using the Guoy-Chapman–Stern technique and the site binding association model. The baseline field-effect transistor (FET) of the ISFET is modeled using Fermi-Dirac statistics to obtain surface potential, which is further used to derive a compact drain current expression. The proposed ISFET model development is carried out by accounting for the interface trap effect. The voltage and current sensitivity of ISFET with and without interface traps are calculated to demonstrate the impact of interface traps in 2-D material-based pH sensors. It is observed that voltage sensitivity remains close to the Nernst limit (59 mV/pH), and a decrease in current sensitivity from 34 to 2 nA/pH is observed, as the density of interface traps is varied from 0 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${5}\times {10} {^{{12}}}$ </tex-math></inline-formula>cm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-}2 $ </tex-math></inline-formula>eV<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-}1 $ </tex-math></inline-formula>. Another sensitivity metric, the transconductance to drain current ratio, is analyzed for its variation with changes in the density of interface traps. The noise level of ISFET in the presence of interface traps is analyzed, and its influence on the minimum resolvable pH is demonstrated. The proposed model prediction closely matches the TCAD simulation data obtained from a calibrated TCAD simulation setup. The model is suitable for implementation in Verilog-A for ISFET-based circuit simulation, and the impact of interface traps on the response time of ISFET-based circuits is also demonstrated.

A functionally enhanced transistor is a potential candidate for further advancing electronics and Moore's law beyond the classical scaling. This chapter discusses these kinds of multifunctional transistors called reconfigurable field-effect transistor (RFET) and reconfigurable tunnel field-effect transistor (RTFET). The RFET works on the principle of Schottky barrier tunneling, and the RTFET works on the principle of band-to-band tunneling. Both devices can be configured as an n-type and p-type device based on the biasing. This chapter explains the working and performance comparison of RFET and RTFET in detail with the help of technology computer-aided design (TCAD) simulations. Further, the potential and current models of a single-gated RFET and double-gated RTFET are presented in this chapter. The presented analytical models are compared and verified with TCAD simulations. The potential in the channel regions of RFET and RTFET is modeled by solving a two-dimensional (2D) Poisson's equation. Because the working principle of both devices is different, two different formulas are utilized for modeling the current in the device. The current model for the RFET is developed by integrating Landauer's formula, whereas the current model for RTFET is obtained by integrating band-to-band generation rate over the tunneling volume. The procedure, technique, and assumptions followed to obtain the potential and current models of RFET and RTFET are detailed in this chapter.