Parasitic bipolar amplification in a single event transient and its temperature dependence

The variations of single event transient (SET) pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor (FinFET) inverter chains with different driven strengths are measured at different temperatures. Three-dimensional (3D) technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature. Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk FinFET technology, resulting in the increase of SET pulse width. On the other hand, the increase of inverter driven strength will change the layout topology, which has a complex influence on the SET temperature effects of FinFET inverter chains. The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

A three-dimensional (3D) technology computer-aided design (TCAD) modeling of guard-drain based on 45-nm CMOS process is presented. Numerical simulations of single-device show that charge collection of the guard-drain technique will higher than that of the conventional technique in different ion incidents. Guard-drain technique fails in helping drain to mitigate single-event transient (SET). Mechanisms of this abnormal phenomenon are analyzed in detail.

In this study, SiGe channel nanosheet field-effect transistor (NSFET) with a novel channel release stopping layer (CRSL), namely CRSL-SiGe NSFET, is proposed to addresses the issue of sub-fin recess during channel release in conventional SiGe (C-SiGe) NSFET. Through a three-dimensional technology computer-aided design (TCAD) simulations, we systematically compare the DC and AC electrical characteristics of C-SiGe and CRSL-SiGe NSFETs. The results show that the proposed CRSL-SiGe NSFET achieves a 16% reduction in gate capacitance (C<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GG</sub>) while maintaining a comparable DC performance to C-SiGe NSFET. Additionally, an obvious improvement in gain of the inverter is achieved under various power. Moreover, the oscillation frequency of ring oscillators is increased and their delay is reduced under various power. These results indicate that CRSL-SiGe NSFET is a promising candidate for suppressing process variations and improving circuit performance in the advanced technology node.

In this study, we investigated the impact of random dopant fluctuation (RDF) on junctionless (JL) fin field-effect transistors (FinFETs) with ferroelectric (FE) negative capacitance (NC) effect. The RDF-induced variations were captured by using built-in Sano methodology in three-dimensional technology computer-aided design (TCAD) simulation. Compared to the regular JL-FinFETs, the variations in JL-FinFETs with NC effect (NCJL-FinFETs) was observed to be less via statistical Monte Carlo analysis, which further enhanced its performance as well. The evaluation and estimation of threshold voltage (V T ), ON-state current (I on ), OFF-state current (I off ), and subthreshold swing (SS) by different FE layer thicknesses indicated reduction in the standard deviations of V T (δV T ) and I on (δI on ) by 34.7% and 7.08%, respectively; the OFF-state current and its standard deviation shrank by approximately three orders of magnitude than the JL-FinFET counterpart. Although δSS was not monotonous, the SS was significantly improved to sub-60 mV/decade. To sum up, the regular JL-FinFETs containing the FE layer as NC effect not only improved the electrical performance, but also led to the resilience of the RDF-induced statistical variability.

The hump behavior of gate-normal nanowire tunnel field-effect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing (SS) and on-current (Ion) because the corners and sides of nanowires (NWs) have different surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature (R) of NWs and reducing gate insulator thickness (Tins).

The radiation effects on a multi-nanosheet tunneling-based field effect transistor (NS-TFET) were investigated for a 3-nm technology node using a three-dimensional (3D) technology computer-aided design (TCAD) simulator. An alpha particle was injected into a field effect transistor (FET), which resulted in a drain current fluctuation and caused the integrated circuit to malfunction as the result of a soft-error-rate (SER) issue. It was subsequently observed that radiation effects on NS-TFET were completely different from a conventional drift-diffusion (DD)-based FET. Unlike a conventional DD-based FET, when an alpha particle enters the source and channel areas in the current scenario, a larger drain current fluctuation occurs due to a tunneling mechanism between the source and the channel, and this has a significant effect on the drain current. In addition, as the temperature increases, the radiation effect increases as a result of a decrease in silicon bandgap energy and a resultant increase in band-to-band generation. Finally, the radiation effect was analyzed according to the energy of the alpha particle. These results can provide a guideline by which to design a robust integrated circuit for radiation that is totally different from the conventional DD-FET approach.

The change of P+ deep well doping will affect the charge collection of the active and passive devices in nano-technology, thus affecting the propagated single event transient (SET) pulsewidths in circuits. The propagated SET pulsewidths can be quenched by reducing the doping of P+ deep well in the appropriate range. The study shows that the doping of P+ deep well mainly affects the bipolar amplification component of SET current, and that changing the P+ deep well doping has little effect on NMOS but great effect on PMOS.

This work presents the characteristics of the single event transient (SET) induced by a single heavy ion in the inverse mode NPN-SiGe HBT simulated with the Silvaco TCAD toolkit. The designed SiGe HBT technology structure was built on the DevEdit simulator and simulated on Deckbuild using device and radiation effect simulations. The characteristics of device SET distribution, including transient pulse current, corresponding collection charge, pulse current peak, and full width at half maximum (FWHM) levels, etc, were simulated and compared as they changed with heavy ion LETs (0.2 pC μm−1 ∼ 1.0 pC μm−1), striking angles (30° ∼ 120°), and device emitter bias voltage settings (0.6 V ∼ 1.8 V). Meanwhile, the electrostatic potential distribution was found to be impacted by the heavy ion SET at the initial time moment when the heavy ion began to strike the surface of the device. The mechanisms for SET variation and its influence on the device potential under different conditions were primarily analyzed and discussed.

We study the performance of vertically stacked InGaAs/InAlAs/InP Double Quantum Well (DQW) Fin Field Effect Transistor (FinFET) on Si substrate using three-dimensional Technology Computer-Aided Design (TCAD) simulation. In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As and In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.52</sub> Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.48</sub> As are used as the quantum well channel and the barrier material, respectively. Both materials are lattice matched to the InP buffer layer material on Si substrate. The device is simulated with gate lengths (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) of 15 nm and gate stack (Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) of 1nm/2nm (EOT~0.75nm). The simulation results reveal that by using double channel quantum well (super lattice structure) can enhance the saturation current up to 24% compared to Single Quantum Well (SQW) device. The maximum capacitance of the DQW also outperforms the SQW FinFET approximately 34%. The higher capacitance indicates the higher carrier density. The electron density of DQW prefers to localize in the InGaAs layer as the quantum well channel, thus allow greater control over the electron behavior. The device characteristics indicate that the DQW FinFET on Si substrate can be alternated to enhance the device performance for prospective high performance logic device applications.

As technology down scales, single event transient (SET) is more vulnerable than before in combinational circuits. This paper proposes a novel layout technique to mitigate the SET effect in combinational circuits. Based on 65nm CMOS process, technology computer aided design (TCAD) SET simulations are conducted on conventional layout, source-isolation layout, dummy transistor layout and the proposed layout. Heavy ions with different liner energy transfer (LET) values, inject angles and striking locations are simulated. The results indicate that, the proposed layout have considerable effect on decreasing the SET pulse width than other layouts. Compare with dummy transistor the proposed enhance dummy transistor have no additional area cost.

The dependence of 0.13µm NMOS single event transient on linear energy transfer (LET) is studied and integrated into a single event transient (SET) pulses fault injection model. A modified double exponential function with four parameters that are related to LET is used to fit the single event transient pulsed current. By translating into the LET-dependent model, it can predict the charge collection without Technology Computer Aided Design (TCAD) simulation when LET is changed. The SRAM unit is built using the proposed single event transient pulses fault injection model into the sensitive node, proving the practicability and reasonableness of the proposed fault injection model for circuit-level single-event effect (SEE) simulation.

When a high energy particle strikes an integrated circuit, the electron-hole pairs generated in the substrate get collected at source/drain regions. The net effect on the circuit is a transient current (single event transient or SET) injected into circuit nodes. This SET can propagate and cause an error in a state register, which is called a single-event upset (SEU). We perform a detailed characterization of the impact of an SET on a logic circuit. We observe that the impact of an SET can be understood only as a two cycle phenomenon, with several possible SEU outcomes. To understand the relative probabilities of these outcomes, we perform a detailed characterization of the impact of an SET using a Monte Carlo sampling scheme which uses post-layout circuit simulations. These simulations were run in 180nm and 65nm technologies with circuits from ISCAS'85 and ITC'99 benchmarks as test cases. Based on these simulations, we observe that all the SEU outcomes are represented to a substantial extent. Further, there is a substantial fraction of outcomes in which the SET affects multiple state registers. This indicates that the traditional view of impact of an SET on a circuit as a single bit-flip and a single cycle phenomenon may not be fully justified. The impact of an SET is in reality, distributed across two cycles and across multiple state register bits.

In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We proposed a flip-flop of SET-SEU-RHBD. This flip-flop has LPF using a C-element with dual transmission and applies an MNL technique only on the master latch. This flip-flop is designed with 45-nm technology and a 16-grid height. Mitigation efficiencies of the flip-flop are estimated by accelerated experiments and simulations. The flip-flop can protect 90% of SEU and 52 ps SET pulse with low penalties.

We propose a physics-based analytical model that accurately captures the effects of buffer traps on dc characteristics of gallium nitride (GaN)-based high-electron-mobility transistors (HEMTs). The model is then semi-analytically extended to additionally include the transient behavior. Analytical formulations for the shift in the threshold voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${(}{V}_{\text {OFF}}{)}$ </tex-math></inline-formula> and two-dimensional electron gas (2-DEG) density due to the presence of buffer traps in the steady state are presented. In pulsed operation, technology computer-aided design (TCAD) simulations indicate that a time-dependent negative potential (NP) is developed under the gate, resulting in a modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {OFF}}$ </tex-math></inline-formula> and current collapse (CC). An expression for the modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {off}}$ </tex-math></inline-formula> helps capture the pulsed current–voltage characteristics. The model captures the dependence of bias, time, temperature, trap concentration, capture cross section area, and activation energy of traps on the steady-state and transient characteristics. The model is implemented in Verilog-A in an existing compact model framework using a diode and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> sub-circuit and validated using measured data and TCAD simulations. The modeling results are in excellent agreement with the experimental data and TCAD simulations. Since the model is physics-based, it requires fewer number of parameters compared to that in the existing models.

&lt;p&gt;The incidence of high-energy particles into the semiconductor device would induce single event transients (SETs), which is a main threaten to MOS device. And the incidence distances and Linear Energy Transfers (LETs) have important effects on the SET current. A machine learning method based on Whale Optimization Algorithm-Back Propagation neural network (WOA-BPNN) model considering injection distances and LETs has been proposed to predict SET current in this paper. And this method could effectively reduce the simulation time from hours to seconds compared to device model. The current data that predicted by this method has been compared with the Technology Computer Aided Design (TCAD) simulation result which obtained in the background of the 40 nm process technology, the regression coefficient between the predicted value based on the proposed method and the TCAD simulation result was 99.76%, and the maximum integral relative error was 0.287% while the minimum integral relative error is 0.04%. Besides, the proposed method is also compared with PSO-BPNN (Particle Swarm Optimization, PSO) and GA-BPNN (Genetic Algorithm, GA), and the results demonstrated that the WOA-BPNN has prediction accuracy and timing saving advantages over the other two methods.&lt;/p&gt; &lt;p&gt; &lt;/p&gt;