A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients

Threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of transistors plays an important role in single-event upsets (SEU) and system power consumption. Effect of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> on single-event upsets can be very different for different technologies. SEU responses of flip-flops and logic circuits in 20-nm bulk planar and 16-nm bulk FinFET technologies with different V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> options are investigated. Results show that for the 20-nm bulk planar technology, the design with the highest threshold voltage among all V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> options shows the lowest SEU cross-section for alpha particle irradiation. For the 16-nm FinFET technology, the option with the highest threshold voltage shows the highest SEU cross-section. As frequency increases, the SEU cross-section of the highest V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> design shows a faster increase and a larger curve slope due to increased single-event transient (SET) pulse width compared to the lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> designs for the 16-nm FinFET technology node.

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

In this paper we describe the fault injection models for the systems tolerant to the single event upsets (SEU) and single event transients (SET). The presented fault modelling approach is based on the random generated SEU faults in sequential logic and SET faults in combinational logic. The fault injection models for triple modular redundant (TMR) and dual modular redundant (DMR) circuits are developed in order to simulate the fault-tolerant systems. The analytical models for calculation of the probability of failure-free TMR and DMR circuits are defined too. To justify the reduced redundancy concept, the simulated and calculated probabilities of failure-free TMR and DMR circuits are presented and discussed. The obtained results show a better trade-off between hardware overhead and circuit failure-free probability of the DMR concept.

Single event upset mitigation by means of a sequential circuit state freeze

In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We proposed a flip-flop of SET-SEU-RHBD. This flip-flop has LPF using a C-element with dual transmission and applies an MNL technique only on the master latch. This flip-flop is designed with 45-nm technology and a 16-grid height. Mitigation efficiencies of the flip-flop are estimated by accelerated experiments and simulations. The flip-flop can protect 90% of SEU and 52 ps SET pulse with low penalties.

A single event transient (SET) filtering technique for non-volatile field programmable gate arrays (FPGAs) are investigated experimentally using the AND-OR-Multiplexer SET filter technique. The technique combines AND – OR gate circuits in parallel with a two input multiplexer to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations in a commercial Flash-based FPGA, the 0.13-μm ProASIC3E product family (A3PE), by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.

Reliability means and radiation resistance of digital equipment. For aerospace computer systems is extremely urgent to develop radiation-resistant components. One way to ensure the radiation resistance is the creation of a special architecture — RHBD (Radiation Hardened by Design). This approach includes triple redundancy (Triple Modular Redundancy — TMR) to reduce radiation-induced switching of logic elements (Single Event Transients — SET) and memory elements (Single Event Upset — SEU). FPGA due to the large number of elements configuration memory is not vulnerable to the effects of radiation. Therefore, one-time programmable devices are used, for example, the companies Actel, but flip-flops tripled too. Nevertheless, in the SRAM configurable FPGA Virtex (Xilinx) used triple redundancy with Majority Vote Circuit based on a tristate buffer instead LUT. Such Voter has implementation features that are explored in the article. One of the variants of majority voter for the pins of the FPGA using a minority voting function. Only in this case, no conflict of signals at the outputs of buffers. Describes CMOS implementation of the voters. The paper proposes a fault tolerant CMOS implementation of the Majority Voter and Minority Voter in order to improve reliability and FPGA radiation resistance.

PurposeThe purpose of this paper is to present a transition detector (TD)-based radiation hardened flip-flop (TDRH-FF) for single event upset (SEU).Design/methodology/approachWith SEU recovery and single event transient (SET) detector mechanism, the TDRH-FF can tolerate SEU during hold mode and generate a warning signal for architecture-level recovery during transport mode when input signal contains SET. Evaluation results show that the TDRH-FF outperforms comparable comprehensive performance.FindingsSimulation results show that 1) the mean pulse width of the correction glitches (at full width half maximum) of TDRH-FF is less than 10 ps; 2) the area overhead of TDRH-FF is similar to the EVFERST-FF, BISER-FF and DNURHL-FF; 3) TDRH-FF has the same average power consumption as SETTOF, and moderate PDP and Ps values among these compared FFs.Originality/valueIn this paper, a TD-based TDRH-FF is proposed to solve the problems in the previous design. And the main contributions of the proposed TDRH-FF are summarized: Minimum size transistors are used in the proposed TD which leads to a considerable decrease in area overheads and propagation delay (resulting in an ignorable correction glitch); and compared with other radiation hardened flip-flop, TDRH-FF outperforms comparable comprehensive performance.

On space missions, software suffers from Single Event Upsets (SEUs), producing bit-flips. A single bitflip can impede the whole program. In this work we present a novel software based approach to tolerate SEUs by redundant execution and protected memory. This approach can protect specifically designed programs against all SEUs. Our aim is to be able to use of-the-shelf processors and other complex circuits by designing appropriately the software and simple hardened devices (e.g. memory). A Linux based simulator has been developed and implemented: it uses, validates and allowed us to refine our hypotheses. A hardware prototype confirmed these results.

The proposed work analyzes the Single Event Transients (SETs) in combinational circuits and Single Event Upsets (SEUs) in sequential elements for 16 nm FinFET device structures implemented using Visual TCAD tool. The FinFET CMOS circuits of traditional and Dual-port Radhard designs are compared for power consumption and particle strike immunity. As the radhard circuits are inherently redundant this causes proportional increase in power consumption which is ~2 times as compared to traditional design. In the presented work, the radiation resilience of the implemented radhard circuits, measured in terms of critical charge (QC), has drastically improved by greater than three order as compared to the traditional designs. With this improvement the radhard designs can in turn withstand an accelerated heavy ion particle strike with Linear Energy Transfer (LET) up to 50 MeV-cm2/μm for SETs and LETs upto 100 MeV-cm2/μm for SEUs. Finally, the Visual TCAD particle strike simulation showed that the radhard FinFET circuits were resilient and adjacent nodes were not affected for increased energy levels.KeywordsFinFETsRadiation hardeningStandard cellTotal Ionizing Dose (TID)Single Event Effects (SEEs)Single Event Upsets (SEUs)LET

Nowadays, FPGAs are used in many safety-critical applications. They are mainly subjected to Single Event Upsets (SEUs) that can flip the state of a memory cell, thereby forcing the circuit to produce an erroneous output. Fault-tolerant techniques are used to mitigate these errors. Triple Modular Redundancy (TMR) is one of the most commonly used fault-tolerant techniques in FPGAs. However, the voter is a single point of failure. This paper proposes a fault secure TMR voter design. This voter is analyzed according to its FPGA implementation. SEUs, Single Event Transients (SETs) as well as single stuck-at-0(1) faults are considered. In the presence of these faults, this voter will always produce the correct output or will give an indication of the presence of an error. Alternating Logic is utilized in the design to help with error detection while Dynamic Partial Reconfiguration (DPR) is used for error recovery.

Single-event transients (SETs) threaten modern reliability-demanding SoCs equipped with error correction codes (ECC) for single event upset (SEU) mitigation. However, conventional gate-level SET fault injection (FI) remains prohibitively slow for practical reliability evaluation. This work presents Flawase, a high-throughput SET injection framework that enables comprehensive system-level evaluation of SET-induced soft errors. Flawase consists of two phases: a netlist-level inject-and-capture simulation, which systematically flips the output of every gate-cycle pair during program execution to record flipflop changes one cycle later, and a scan-chain-based replay-andmeasure emulation, which replays these patterns at hardware speed to quantify system-level impact. Implemented on an opensource RISC-V system, FIawase reduces a comprehensive SET injection campaign from decades of pure simulation to nearly a day, achieving over four orders of magnitude end-to-end speedup. Flawase takes a critical first step toward exhaustive, cycle-accurate SET analysis, enabling architectural and reliability research at previously infeasible scales.

This paper proposes soft error immune flip-flop (SEIFF) for mitigating single event upset (SEU) in flip-flops (FFs) and impact of single event transient (SET) in combinational-logic. SEIFF mitigates the SET without enlarging setup-time and delay; there is no overhead in circuit performance. Alpha and proton tests validate the mitigation efficiency in SEIFF manufactured on 10 nm FinFET technology.

Using three-dimensional technology computer-aided design (TCAD) simulation, parasitic bipolar amplification in a single event transient (SET) current of a single transistor and its temperature dependence are studied. We quantify the contributions of different current components in a SET current pulse, and it is found that the proportion of parasitic bipolar amplification in total collected charge is about 30% in both 130-nm and 90-nm technologies. The temperature dependence of parasitic bipolar amplification and the mechanism of the SET pulse are also investigated and quantified. The results show that the proportion of charge induced by parasitic bipolar increases with rising temperature, which illustrates that the parasitic bipolar amplification plays an important role in the charge collection of a single transistor.

We present a formal approach to minimize the number of voters in triple-modular redundant (TMR) sequential circuits. Our technique actually works on a single copy of the TMR circuit and considers a large class of fault mo dels of the form “at most 1 Single-Event Upset (SEU) or Single-Event Transient (SET) every k clock cycles”. Verification-based voter minimization guarantees that the resulting TMR circuit (i) is fault tolerant to the soft-errors defined by the fault model and (ii) is functionally equivalent to the initial TMR circuit. Our approach operates at the logic level and takes into account the input and output interface specifications of the circuit. Its implementation makes use of graph traversal algorithms, fixed-point iterations, and binary decision diagrams (BDD). Experimental results on the ITC’99 benchmark suite indicate that our method significantly decreases the number of inserted voters, yielding a hardware reduction of up to 55% and a clock frequency increase of up to 35% compared to full TMR. As our experiments show, if the SEU fault-model is replaced with the stricter fault-model of SET, it has a minor impact on the number of removed voters. On the other hand, BDD-based modelling of SET effects represents a more complex task than the modelling of an SEU as a bit-flip. We propose solutions for this task and explain the nature of encountered problems. We address scalability issues arising from formal verification with approximations and assess their efficiency and precision.