Machine learning based effective linear regression model for TSV layer assignment in 3DIC

The X Architecture is an integrated-circuit wiring architecture based on the pervasive use of diagonal wires. Compared with the traditional, currently ubiquitous, Manhattan architecture, the X Architecture demonstrates a wire length reduction of more than 20% and a via reduction of more 30%. Because of the rapidly increasing percentage of delay due to interconnect and the manufacturing challenges due to vias in the nanometer realm, these length and via reductions result simultaneously in a chip performance improvement of 10%, a power reduction of 20%, and a die cost reduction of 30%. Furthermore, the reduction in both wire length and parallel runs on different layers often both reduces die size and improves signal integrity. Remarkably, on virtually every important measure of chip quality, the X Architecture is superior to the Manhattan architecture.While diagonal wiring has been discussed for years, and short diagonal jogs have even been used for years, pervasive diagonal wiring has not been used on an IC before 2002 (to our knowledge). The fundamental reasons for this are not manufacturing limitations, as might be suspected, but EDA limitations, and the changes required to take full advantage of the X Architecture are significant and numerous. In particular, routing must be not only octilinear, but also gridless and non-preferred direction. In addition, significant changes are required at least in floorplanning, placement, global routing, extraction, power routing, clock routing, wire length estimation (e.g., in synthesis), database, graphics, and even data interchange formats. The folklore that 45-degree wiring might not be worth the trouble because it can provide only a 10% reduction in wire length is rooted in the incorrect assumptions that (a) only the router must change, (b) the router must resemble contemporary, preferred-direction, net-at-a-time maze routers, and (c) that wire length is the only major contributor to interconnect delay.In this short paper, we present some of the challenges and opportunities afforded by the X Architecture and show some early results that demonstrate the promise of pervasive, diagonal wiring, reflecting our belief that five years from now, virtually all, high-performance, integrated circuits will use the X Architecture.

Channel routing problem of area minimization is a well-defined problem in VLSI physical design automation. In this paper we have developed algorithms for computing reduced wire length channel routing solutions using a purely graph theoretic framework, TAH (track assignment heuristic) that was designed for computing minimum area routing solutions. Here we consider the total wire length of a routing solution as one of the most important factors of high performance computing. Reduction in wire length is important from signal delay as well as from the viewpoint of cost of wire segments required in interconnecting all the nets. The framework is designed for computing routing solutions in two-layer channels, and extended to route three-layer routing also in a modular fashion. All the algorithms developed under the framework of TAH are executed for computing no-dogleg and dogleg routing solutions for most of the well-known benchmark channels, with reduced total area and/or total wire length in two- and three-layer channel routing. Performance of our algorithms is highly encouraging.

Current design of 3L SOT223 leadframe would allow for a long bonding wires due to its large die attach flag design as compared to the die size. Long bonding wires have resulted in a number of subsequent process and assembly related problem such as wire sway, wire shorting and lifted wire. One way to reduce the wire length is by reducing the die attach pad (flag) size and at the same time redesigning the leads so they are extended into the package center. By doing this, the second bond positions on the lead are closer to the first bond on the die. This reduction in wire length would ultimately result in improved wire strength and integrity especially during epoxy mold compound flow sweeping on these wires. It would also results in cost saving by reducing the amount of wire used per unit of package. The new design has also resulted in reduced usage of copper material for the leadframe. However, it is suspected that the reduction in flag size will change the way stress acting on the die when mechanical and thermal stresses acting onto the package due to reduced contact area between the flag and mold compound. The need to study the effect of reducing the die attach flag on the die stress has prompted this study, which is to investigate if the proposed changes as mentioned above will result in a better stress performance of the die as compared to the current leadframe design. The approach used in this study is by using finite element analysis (FEA) modeling tool and doing reliability data to support the finding of the FEA analysis. The existing leadframe was designed with several locking features added to reduce thermal and mechanical stress on the die especially at trim and form process. These locking features are in the form of two round-shaped through hole and few v-grooves on all leads and the tab. Initial findings suggest that the new leadframe design would result in higher stress level especially due to mechanical loading, compared to the existing leadframe. This initial finding is based on the new leadframe with similar locking features (size and position) as the existing leadframe. Further analysis of the locking features has resulted in optimized locking features in terms of size and dimension, which resulted in leadframe with better stress performance compared to the existing leadframe. Reliability data fully supports this finding with improved delamination and other reliability indexes were achieved. This paper will discuss in great detail the approach used in solving the issue, the various design option considered as well as the optimization work and related engineering theory. It concludes that with optimized locking features, the new leadframe can perform equally better compared to existing leadframe, and more importantly, at the same time the requirement of shorter wire is met.

With the standard approach for establishing multicast connections over a network, network nodes are utilized to forward and duplicate the packets received over the incoming links. Recently, there has been a significant interest in a novel paradigm of network coding. Network coding generalizes the traditional routing approach by allowing the network nodes to generate new packets by performing algebraic operations on packets received over the incoming links. It has been shown that network coding can increase the throughput of multicast communication. In this paper, we explore the benefits of network coding for improving the routing characteristics of VLSI designs. We demonstrate that when data has to be routed across the IC, it is often beneficial to perform network coding. Initial results demonstrate that network coding can result in a healthy reduction in wire length, wire area, interconnect power as well as the active area associated with the interconnects. This comes at a small delay penalty.

Three-dimensional integrated circuits hold great promise for performance improvement and power savings through the reduction of footprint and wire length. However, the technology comes with new challenges especially in the early design stages. One such challenge is the development and use of adequate floorplan representations. Another challenge is the accounting for thermal stress during the physical design stage of 3D integrated circuits. Contrasted with the conventional, layerwise 2D floorplanning approaches, genuine 3D layout representations naturally integrate vertical relations between layers. In this paper, we present a design flow that integrates 3D floorplanning with thermal awareness based on the use of native 3D layout representations. The floorplanning phase accounts for wirelength and chip area while the thermal verification phase use the insertion of thermal through silicon vias (TSVs) to reduce the number and magnitudes of hot spots. The main contribution of this paper is the integration of both phases within an iterative loop based on native 3D layout data structures. The impact of thermal TSV insertion strongly increases with the number of chip layers. We show that as little as 0.5% average TSV density can decrease the maximum chip temperature by 15, 45 and 90 degrees for two, three and four layer configurations of exemplary 3D designs, respectively. The presented approach paves the way for thermal-driven design methods that profit from the 3D representations of layouts made of several stacked layers.

3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphite-based heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45μC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.

Background: The air quality of any area depends upon the various PMs (particulate matter) and hazardous gases present in the air. Low-cost PM sensors and gas sensors are present in different target places to monitor the air quality, read the environmental data, and transmit it to local servers through the IoT device. The low-cost sensor is not reliable due to its low sensing capacity; therefore, the read data is calibrated with the meteorological data presented by the nearby meteorological Centre of that particular area. The calibrated reading data sent to the server could be analyzed through some Machine Learning [ML] models. The ML models help to predict the risk of asthma in a particular area. The risk of asthma is directly related to the air quality of the surroundings. It is observed that the air quality of the industrial area is much worse than the non-industrial belt. Air quality monitoring of industrial areas is always a challenging task due to the ununiformed pollution in some segregated places around the industry, emitting pollutants mostly from chimneys. The air quality of any area depends upon the PM (PM), i.e., PM2.5 and PM10.0, as well as the gasses like NO2(Nitrogen Dioxide), NH3 (Ammonia), SO2(Sulfur dioxide), CO(Carbon monoxide), O3(Ozone) and Benzene. These are the most hazardous gases generally emitted by common heavy industries like iron and steel. In this article, the researchers considered the industrial belt of the Asansol- Durgapur region of West Bengal, India, and predicted the risk of asthma attacks for the test dataset. The experiment was carried out on 10 different supervised machine learning [SML] models as well as semi-supervised machine learning (SSML) models. The SML models have been further refined through hyper-parameter tuning, and better results have been obtained in the case of some ML models. The result has been compared with the existing literature considering the same external environment from where the meteorological data was collected, and similar ML models have been used. The research outperformed the existing literature, which is depicted in the result and analysis section of the article. Methods: The study evaluated ML models, both supervised and semi-supervised, to assess pollution levels. Relevant features were selected while less relevant ones were discarded. Accuracy levels of different ML algorithms werecompared in the results. The most effective model for an IoT system was chosen to maximize accuracy. In semi-supervised learning, feature selection followed supervised learning, but testing was akin to unsupervised learning. Results were compared with supervised learning data, enhancing reliability. Results: The result employing various classifiers werepresented across tables after the independent parameter Ozone was removed. Following the output of several classifiers, the results were verified using the k-fold validation method, with k being set to 5 or 10, accordingly. Tables display the best outcome, which is indicated in bold characters. method: In this research work the researcher considered 9 different ML models and used them as supervised as well as semi supervised model to determine the pollution level of the certain area. In this research work the researcher also selected the most relevant features and discarded the less relevant features. In case of SML algorithm, the accuracy level of the different ML algorithm has been determined and depicted in the result analysis section. The most effective ML model has been chosen for the proposed embedded system so that accuracy could be achieved at most. In case of semi supervised algorithm the feature selection is done as per the supervised algorithm. In this case the training is done same as the SML algorithm, but the testing phase is done like unsupervised machine learning algorithm where the decision parameter is predicted and ultimately matched with the previously achieved data of SML algorithm. The reliability of this approach is much more effective than simple SML algorithm. Conclusion: This study focused on predicting asthma risk in the Asansol-Durgapur industrial belt, India, using low-cost PM and gas sensors. Data calibration with meteorological inputs enhanced accuracy. ML models predicted risk and were refined through hyper-parameter tuning. Comparative analysis showed superior performance, emphasizing the importance of precise air quality monitoring. While offering a robust framework for future research, the study’s limitation lies in its area-specific dataset.

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

Footprint scaling may reduce wire lengths when more metal layers are available for routing. To achieve optimal wire length, footprint should be very small in which case pin density will be extremely high. However, high pin density may lead to detailed routing failure. We demonstrate that there is a threshold pin density beyond which standard routing heuristics fail to access pins on the bottom layer, even with unlimited number of metal layers available for routing. Future technologies, such as vertical slit field-effect transistor (VeSFET), may have layouts with pin density exceeding the threshold. We show that VeSFET layouts are still routable within footprint using two-sided routing. Compared to one-sided routing, two-sided routing achieves shorter wire lengths and fewer vias, hence lower interconnect capacitance and better performance.

This paper forwards a novel wire length calculation algorithm based on TSV position. Typical 2D wire length calculation method such as half-perimeter model does not take via position into account. But in 3D IC placement, TSV position does affect the real wire length which is ignored in previous works. To get accurate wire length data and help 3D placement researches, this paper forwards the TSV based 3D IC wire length algorithm. Experiments are done on folded placement results of IBM placement benchmark circuits. Results shows that this algorithm can effectively identify the difference wire length of the cross wafer net according to the traditional method and calculate it accurately.

Machine learning (ML) has become a robust method for modeling field operations based on measurements. For example, wellbore cleanout is a critical operation that needs to be optimized to enhance the removal of solids to reduce problems associated with poor hole cleaning. However, as wellbore geometry becomes more complicated, it gets more difficult to predict the cleaning performance of fluids. As a result, optimization is often challenging. Therefore, this study aims to develop a data-driven model for predicting hole cleaning in deviated wells to optimize drilling performance.More than 500 flow loop measurements from 8 studies are used to formulate a suitable ML model to forecast hole cleanout in directional wells. Measurements were obtained from hole-cleaning experiments that were conducted using different loop configurations. Test sections ranged in length from 22 to 100 feet, in hole diameter from 4 to 8 inches, and in pipe diameter from 2 to 4.5 inches. The experiments provided measured equilibrium bed height at a specific flow rate for various fluids, including water-based and oil-based fluids and fluids containing fibers. Several relevant test parameters, including fluid and cutting properties, well inclination, and drilling string rotation speed, were also considered in the analysis. The collected data has been analyzed using the Cross-Industry Standard Process for Data Mining (CRISP-DM). Six different machine learning techniques (Random Forest, Linear Regression, Neural Networks, Multivariate Adaptive Regression Spline, Support Vector Machine, and Boosted Decision Tree) have been evaluated to select the most appropriate method for predicting bed thickness in a wellbore. Also, we compared the predictions of the selected ML method with those of a mechanistic model for cases without drill string rotation. Finally, using the ML model, a parametric study has been conducted to investigate the impact of various parameters on the cleanout performance of selected fluids.Results show the relative influence of different variables on the prediction of cuttings bed. Accordingly, flow rate, drill string rotation, and fluid behavior index have a strong impact on dimensionless bed thickness, while other parameters such as fluid consistency index, solids density and diameter, fiber concentration, and well inclination angle have a moderate effect. The Boosted Decision Tree algorithm has provided the most accurate prediction with an R-square of approximately 90%, Root Mean Square Error (RMSE) of close to 0.07, and Mean Absolute Error (MAE) of roughly 0.05. A comparison between a mechanistic model and the selected ML technique shows that the ML model provided better predictions.

Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed to facilitate DFT (Design-For-Test). Recently, three-dimensional (3D) technologies have been proposed as a promising solution to continue technology scaling. In this paper, we study the scan chain construction for 3D ICs, examining the impact of 3D technologies on scan chain ordering. Three different 3D scan chain design approaches (namely, VIA3D, MAP3D, and OPT3D) are proposed and compared, with the experimental results for ISCAS89 benchmark circuits. The advantages as well as disadvantages for each approach are discussed. The results show that both MAP3D and VIA3D approaches require no changes of 2D scan chain algorithms, but OPT3D can achieve the best wire length reduction for the scan chain design. The average scan chain wire length of six ISCAS89 benchmarks obtained from OPT3D has 46.0% reduction compared to the 2D scan chain design. To the best of our knowledge, this is the first study on scan chain design for 3D integrated circuits.

Three-dimensional integrated circuits gain more and more attention due to their benefits in wirelength reduction and their potential for heterogeneous integration of systems on a chip. Besides the advantages they also lead to new challenges and increasing complexity in designing such systems. This paper focuses on floorplanning such systems. It describes a new data structure called T∗-tree which enables the design of three-dimensional integrated circuits considering vertically aligned rectilinear 2D modules. The problem formulation of the new T∗-tree differs from the T-tree proposed in [1]. Furthermore, an optimization algorithm is presented which is aware of fixed-outline constraints using a longest path based method. Experimental results show that the T∗-tree is competitive to other approaches. It is also able to consider more appropriate modules for three-dimensional integration.

The rise of three-dimensional (3D) IC layouts necessitates the development of unique partitioning methods that will be suitable for the 3D component designs. Net lists partitioning is a key aspect of the physical design of a 3D IC. Reducing wire lengths between gates is possible with 3D-ICs since they have a small footprint as well as vertical connectivity among dies. As a result, they consume less power and have shorter connection delays. This paper presents an efficient genetic algorithm (GA) based layer partitioning technique for 3D ICs that focuses on proper layer assignment to reduce area deviation and minimization of Through Silicon Vias (TSVs) to reduce IC footprint. The method starts with random initial solutions and refines the solutions with efficient crossover and mutation operator till the optimized solution is achieved. Our methodology produces high-quality solutions on well-known benchmarks. The experimental findings are compared with state-of-the-art methodologies and the suggested strategy is found to be very effective in the case of decreasing the TSV count and space need of the 3-dimensional IC design. In addition, the performance of our strategy is also compared with two recent publications that use GA and Particle Swarm Optimization (PSO) and it is found that the proposed method achieves 20.18% and 38.66% average reduction in terms of TSV count respectively. Thus, the suggested technique is beneficial for multilayered 3D IC partitioning, as it can reduce TSV count while also satisfying balancing criteria and latency.

Spatiotemporal time series prediction plays a crucial role in a wide range of applications. However, in most of the studies, spatial information was ignored and predictions were carried out either on a few points or on average values. In this study, 37 different configurations of 4 traditional ML models and 3 Neural Network (NN) based models were utilized to provide a comprehensive comparison and evaluate the spatiotemporal data prediction capabilities of the ML models. Additionally, to reveal the importance of spatial data for the time series prediction process, the best configuration of each ML model was evaluated with and without using spatial information. The utilized models were: (i) Linear Regression (LR), (ii) K-Nearest Neighbors (KNN), (iii) Decision-Trees (DT), (iv) Support Vector Machine (SVM), (v) Multi-Layer Perceptron (MLP), (vi) Long Short-Term Memory (LSTM), and (vii) Gated Recurrent Unit (GRU). The study was performed on the Sea Surface Temperature (SST) data collected by satellite radiometers via infrared measurements. The models were evaluated according to their one-month ahead spatiotemporal SST prediction performance over the southern coasts of Turkey, and the effects of spatial information on model performance were presented. Results reveal that the spatial information increased the prediction performance by approximately 25%, in terms of RMSE. Additionally, acquired results show that the LSTM model outperforms all other ML models and gives the smallest prediction errors in all metrics.