Routing Challenges for Designs With Super High Pin Density

Abstract. The recently introduced Vertical Slit Field Effect Transistor allows for adjusting its threshold voltage through independent controllable gates. This feature can be applied to a broad range of circuits. In this paper two examples are presented. First, a ring oscillator with a wide frequency tuning range and second, a Schmitt trigger with a controllable hysteresis.

Power wall has become one of the main bottlenecks of future VLSI designs. A recently proposed junctionless twin-gate Vertical Slit Field Effect Transistor (VeSFET) is a low power and thermal friendly device, with highly regular layout, and two-side accessibility. These properties are critical for advanced 2D/3D technologies. SRAMs are fundamental blocks of VLSI systems, which are usually used for technology evaluation. This paper provides a VeSFET SRAM performance assessment modeled by CACTI, a cache modeling tool. The results show that VeSFET SRAM design is speed competitive to CMOS SRAM with about 40% of dynamic read energy consumption and 35% of total power consumption for read access rate 100MHz.

The X Architecture is an integrated-circuit wiring architecture based on the pervasive use of diagonal wires. Compared with the traditional, currently ubiquitous, Manhattan architecture, the X Architecture demonstrates a wire length reduction of more than 20% and a via reduction of more 30%. Because of the rapidly increasing percentage of delay due to interconnect and the manufacturing challenges due to vias in the nanometer realm, these length and via reductions result simultaneously in a chip performance improvement of 10%, a power reduction of 20%, and a die cost reduction of 30%. Furthermore, the reduction in both wire length and parallel runs on different layers often both reduces die size and improves signal integrity. Remarkably, on virtually every important measure of chip quality, the X Architecture is superior to the Manhattan architecture.While diagonal wiring has been discussed for years, and short diagonal jogs have even been used for years, pervasive diagonal wiring has not been used on an IC before 2002 (to our knowledge). The fundamental reasons for this are not manufacturing limitations, as might be suspected, but EDA limitations, and the changes required to take full advantage of the X Architecture are significant and numerous. In particular, routing must be not only octilinear, but also gridless and non-preferred direction. In addition, significant changes are required at least in floorplanning, placement, global routing, extraction, power routing, clock routing, wire length estimation (e.g., in synthesis), database, graphics, and even data interchange formats. The folklore that 45-degree wiring might not be worth the trouble because it can provide only a 10% reduction in wire length is rooted in the incorrect assumptions that (a) only the router must change, (b) the router must resemble contemporary, preferred-direction, net-at-a-time maze routers, and (c) that wire length is the only major contributor to interconnect delay.In this short paper, we present some of the challenges and opportunities afforded by the X Architecture and show some early results that demonstrate the promise of pervasive, diagonal wiring, reflecting our belief that five years from now, virtually all, high-performance, integrated circuits will use the X Architecture.

Channel routing problem of area minimization is a well-defined problem in VLSI physical design automation. In this paper we have developed algorithms for computing reduced wire length channel routing solutions using a purely graph theoretic framework, TAH (track assignment heuristic) that was designed for computing minimum area routing solutions. Here we consider the total wire length of a routing solution as one of the most important factors of high performance computing. Reduction in wire length is important from signal delay as well as from the viewpoint of cost of wire segments required in interconnecting all the nets. The framework is designed for computing routing solutions in two-layer channels, and extended to route three-layer routing also in a modular fashion. All the algorithms developed under the framework of TAH are executed for computing no-dogleg and dogleg routing solutions for most of the well-known benchmark channels, with reduced total area and/or total wire length in two- and three-layer channel routing. Performance of our algorithms is highly encouraging.

Machine learning based effective linear regression model for TSV layer assignment in 3DIC

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices.

Increasing IC complexity is placing new demands on multichip module (MCM) test engineers. Traditional bed of nails and flying test methods are not adequate to meet the demands of high pin count and density. Design tools need to keep pace with new test methods being employed to address this rising complexity. One approach to solving this problem is the use of a membrane test head. This paper discusses the design software requirements and CAD challenges that result from the membrane approach to substrate test. Some of these new challenges include data translation, test probe assignment and optimization, routing, and inner layer testing. The test methods and design requirements discussed are applicable to multichip, few-chip and ball grid array (BGA) packaging.

Vertical field effect transistors (VFETs) using graphene and transition metal dichalcogenide (TMD) heterostructures are promising for downsizing the channel length to a monolayer TMD thickness of 0.65 nm. However, graphene/monolayer TMD/metal VFETs struggle with a low on/off ratio due to gate field screening by the graphene layer and a high off-state tunneling current caused by the large contact area. Here, we propose a 0.65 nm channel length VFET with a very high on/off current ratio made by cross-stacking top and bottom carbon nanotubes (CNTs) with a monolayer TMD in between. The ultranarrow junction area in the CNT/monolayer TMD/CNT VFET can significantly reduce the off-state tunneling current. Additionally, the gate field is transmitted from the sidewall of the bottom CNT to the monolayer MoS2 vertical channel between the two CNTs without field screening, achieving very strong gate modulation. As a result, our devices exhibit about 105 times higher on/off ratio (a maximum of 106), 105 times lower off current (10-13 A), and 560 times lower subthreshold swing (SS) (125 mV dec-1) compared to graphene/monolayer TMD/metal VFETs. In the comparison between multilayer MoS2 and monolayer MoS2 VFETs, rigid multilayer MoS2 forms a large air gap at the multilayer MoS2/CNT/substrate, which reduces electric field transmission. In contrast, monolayer MoS2 bends significantly along the sidewall of the CNT, resulting in minimal air gap formation and enhancing the electric field effect in the channel. As a result, the CNT/monolayer MoS2/CNT VFET shows a 10 times higher on-current saturation and on/off ratio compared to the CNT/multilayer MoS2/CNT VFET.

Vertical low-voltage indium-tin oxide field-effect transistors (FETs) gated by microporous SiO2-based solid electrolyte are fabricated at room temperature. Our results indicate that Li ions can enhance the electric-double-layer capacitance of the microporous SiO2 solid electrolyte and reduce the operation voltage of the vertical FETs from 1.5 to 0.8 V. Such vertical low-voltage FETs exhibited a good performance with a high current output (∼1.0 A/cm2), a low subthreshold swing (<80 mV/decade), and a large on-off ratio (>106), respectively. An operation mechanism which provides a better insight into the oxide-based vertical FETs is discussed.

Current design of 3L SOT223 leadframe would allow for a long bonding wires due to its large die attach flag design as compared to the die size. Long bonding wires have resulted in a number of subsequent process and assembly related problem such as wire sway, wire shorting and lifted wire. One way to reduce the wire length is by reducing the die attach pad (flag) size and at the same time redesigning the leads so they are extended into the package center. By doing this, the second bond positions on the lead are closer to the first bond on the die. This reduction in wire length would ultimately result in improved wire strength and integrity especially during epoxy mold compound flow sweeping on these wires. It would also results in cost saving by reducing the amount of wire used per unit of package. The new design has also resulted in reduced usage of copper material for the leadframe. However, it is suspected that the reduction in flag size will change the way stress acting on the die when mechanical and thermal stresses acting onto the package due to reduced contact area between the flag and mold compound. The need to study the effect of reducing the die attach flag on the die stress has prompted this study, which is to investigate if the proposed changes as mentioned above will result in a better stress performance of the die as compared to the current leadframe design. The approach used in this study is by using finite element analysis (FEA) modeling tool and doing reliability data to support the finding of the FEA analysis. The existing leadframe was designed with several locking features added to reduce thermal and mechanical stress on the die especially at trim and form process. These locking features are in the form of two round-shaped through hole and few v-grooves on all leads and the tab. Initial findings suggest that the new leadframe design would result in higher stress level especially due to mechanical loading, compared to the existing leadframe. This initial finding is based on the new leadframe with similar locking features (size and position) as the existing leadframe. Further analysis of the locking features has resulted in optimized locking features in terms of size and dimension, which resulted in leadframe with better stress performance compared to the existing leadframe. Reliability data fully supports this finding with improved delamination and other reliability indexes were achieved. This paper will discuss in great detail the approach used in solving the issue, the various design option considered as well as the optimization work and related engineering theory. It concludes that with optimized locking features, the new leadframe can perform equally better compared to existing leadframe, and more importantly, at the same time the requirement of shorter wire is met.

With the standard approach for establishing multicast connections over a network, network nodes are utilized to forward and duplicate the packets received over the incoming links. Recently, there has been a significant interest in a novel paradigm of network coding. Network coding generalizes the traditional routing approach by allowing the network nodes to generate new packets by performing algebraic operations on packets received over the incoming links. It has been shown that network coding can increase the throughput of multicast communication. In this paper, we explore the benefits of network coding for improving the routing characteristics of VLSI designs. We demonstrate that when data has to be routed across the IC, it is often beneficial to perform network coding. Initial results demonstrate that network coding can result in a healthy reduction in wire length, wire area, interconnect power as well as the active area associated with the interconnects. This comes at a small delay penalty.

Two-dimensional material-based vertical field-effect transistors (VFETs) have recently garnered significant attention for their potential to enable straightforward formation of ultrashort channel lengths below a nanometer. However, their performance is often limited by unintended leakage currents arising from negative threshold voltages (Vth) and the existence of gate-field-free regions (GFFRs). To address this challenge, leakage currents through the GFFRs must be effectively suppressed under a zero gate bias. In this study, we demonstrate high-performance n-channel MoSe2 VFETs with effective leakage current suppression through GFFRs, achieving on/off current ratios exceeding 105. A vacuum pre-annealing process enables the formation of a low-defect-density MoSe2 channel with a near-zero Vth, thereby significantly reducing the leakage currents. Furthermore, the integration of high-work-function VSe2 as a drain electrode forms a defect-free van der Waals contact, suppressing the tunneling currents in the gate-modulated region. As a result, the defect-engineered MoSe2 VFET exhibited an on/off ratio that was 3 orders of magnitude higher than that of the leakage-prone MoS2 VFET. These findings provide valuable insights into charge transport mechanisms and defect-suppression strategies, laying the foundation for advancements in next-generation VFET technologies.

We present the design and the performance evaluation of a new interconnect for large-scale densely packed electronically scanned antenna arrays that utilize a high-speed digital board-to-board vertical connector. The application targets microwave tissue, imaging in the frequency range from 3 GHz to 8 GHz. The tissue-imaging arrays consist of hundreds of active antenna elements, which require low-reflection, low-loss, and low-crosstalk connections to their respective receiving and transmitting circuits. The small antenna size and the high array density preclude the use of coaxial connectors, which are also expensive and mechanically unreliable. Modern board-to-board high-speed connectors promise bandwidths as high as 12 GHz, along with high pin density, mechanical robustness, and low cost. However, their compatibility with the various transmission lines leading to/from the miniature printed antenna elements and microwave circuitry is not well studied. Here, we focus on the design of the transitions from coplanar waveguide transmission lines to/from a high-speed vertical connector. The performance of the interconnect is examined through electromagnetic simulations and measurements. Comparison is carried out with the expensive sub-miniature push-on sub-micro coaxial connectors commonly used in miniature radio-frequency electronics. The results demonstrate that high-speed vertical connectors can provide comparable performance in the UWB frequency range.

This paper presents the analytical and experimental results of the first successful SGEMP photon test on large, multiwire satellite cables and high pin density, flight-qualified connectors. These cables and connectors were specifically designed for light-weight, high RF attenuation characteristics and low SGEMP response. The cable configurations evaluated included straight, two connector types as well as a large cable bundle wi th branches. The cable composition consisted of plain, unshielded wires contained within a single overshield and a core of plain, unshielded wires and twisted shielded pairs (TSP). The complexity of the cables ranged from 37, 61 and 98 wires. These configurations, compositions and complexities are typical of those found in actual satellite electrical systems. The complete distribution of SGEMP wire currents was measured for each cable tested and compared to the results predicted by an analytical model. The SGEMP response of the high pin density, flight connectors was also measured. The effects of multiwire coupling in the cables was evaluated and compared to the results predicted by a worst case analytical model based on cable core and individual wire capacitances.

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.