Performance assessment of VeSFET-based SRAM

Abstract. The recently introduced Vertical Slit Field Effect Transistor allows for adjusting its threshold voltage through independent controllable gates. This feature can be applied to a broad range of circuits. In this paper two examples are presented. First, a ring oscillator with a wide frequency tuning range and second, a Schmitt trigger with a controllable hysteresis.

Footprint scaling may reduce wire lengths when more metal layers are available for routing. To achieve optimal wire length, footprint should be very small in which case pin density will be extremely high. However, high pin density may lead to detailed routing failure. We demonstrate that there is a threshold pin density beyond which standard routing heuristics fail to access pins on the bottom layer, even with unlimited number of metal layers available for routing. Future technologies, such as vertical slit field-effect transistor (VeSFET), may have layouts with pin density exceeding the threshold. We show that VeSFET layouts are still routable within footprint using two-sided routing. Compared to one-sided routing, two-sided routing achieves shorter wire lengths and fewer vias, hence lower interconnect capacitance and better performance.

A superjunction GaN-based vertical heterojunction field effect transistor with ununiformly doped buffer (UDSJ-VHFET) is proposed in this paper. In contrast to the conventional superjunction vertical heterojunction field effect transistor (SJ-VHFET), the doping density of n-pillar increases linearly from top to bottom, while the p-pillar is split into three regions: linearly doped top region, uniformly doped middle region and linearly doped bottom region. The ununiform doping profile suppresses the increase of electric field peak due to the imbalanced charge and smooths the electric field distribution, thus leads to an increase of the breakdown voltage (Vbr) under charge imbalance condition. Simulation results show that with the doping dose of p-pillar 40% lower (higher) than that of the n-pillar, the Vbr and on-state resistance (Ron) of the proposed device are 6863 V and 4.25 mΩ cm2 (5751 V and 4.32 mΩ cm2), comparing with 3205 V and 4.03 mΩ cm2 (2175 V and 4.10 mΩ cm2) for the conventional SJ-VHFET. Additionally, the proposed device shows a Vbr of 12280 V and Ron of 4.29 mΩ cm2 under charge balance condition, comparing with 12874 V and 4.07 mΩ cm2 for the conventional SJ-VHFET.

The luminescence intensity regulation of organic light-emitting transistor (OLED) device can be achieved effectively by the combination of graphene vertical field effect transistor (GVFET) and OLED. In this paper, we fabricate and characterize the graphene vertical field-effect transistor with gate dielectric of ion–gel film, confirming that its current switching ratio reaches up to 102. Because of the property of high light transmittance in ion–gel film, the OLED device prepared with graphene/PEDOT:PSS as composite anode exhibits good optical properties. We also prepare the graphene vertical organic light-emitting field effect transistor (GVOLEFET) by the combination of GVFET and graphene OLED, analyzing its electrical and optical properties, and confirming that the luminescence intensity can be significantly changed by regulating the gate voltage.

Organic field-effect transistors (OFETs) have shown great potential for applications that require low temperature deposition on large and flexible substrates. To increase their performance, in particular a high transconductance and transit frequency, the transistor channel length has to be scaled into the submicrometer regime, which can be easily achieved in vertical organic field effect transistors (VOFETs). However, despite high performance observed in VOFETs, these transistors usually suffer from short channel effects like weak saturation of the drain current and direct source-drain leakage resulting in large off currents. Here, we study the influence of the injection barrier at the source electrode on the OFF currents, on/off ratio, and transconductance of vertical OFETs. We use two semiconducting materials, 2,6-diphenyl anthracene (DPA), and C60 to vary the injection barrier at the source electrode and are able to show that increasing the Schottky barrier at the source electrode can decrease the direct source/drain leakage by 3 orders of magnitude. However, the increased injection barrier at the source electrode comes at the expense of an increased contact resistance, which in turn will decrease its transconductance and transit frequency. With the help of a 2D drift-diffusion simulation we show that the trade-off between low off currents and high transconductance is inherent to the current VOFET device setup and that new approaches have to be found to design VOFETs that combine good switching properties with high performance.

In this letter, a p-type organic material from metal phthalocyanine (MPc) derivative, vanadyl 3,10,17,24-tetra-tert-butyl-1,8,15,22-tetrakis (dimethylamino)-29H,31H-phthalocyanine (VTP) has been utilized for fabrication of an organic electronic device. Prior to the fabrication of a vertical organic field effect transistor (VOFET), fundamental work in investigating the energy level of VTP has been done through determination of oxidation and reduction potentials. Energy levels of VTP were calculated based on the highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) of cyclic voltammetry (CV) and UV–vis analyses. Subsequently, the soluble VTP was employed as an active layer in VOFET with different thicknesses of 90.4 nm, 66.4 nm, and 52.1 nm. It is found that a device with 66.4 nm VTP’s thickness showed the optimum performance, by giving the maximum current density and lowest threshold voltage of around 37 mA/cm2 and 7.1 V, respectively. The effects of the channel thickness on the semi-transparent VOFET devices are explained in this work.

Vertical organic field effect transistors having a patterned source electrode and an a-SiO2 insulation layer show high performance as a switching element with high transfer characteristics. By measuring the low field magneto-conductance under ambient conditions at room temperature, we show here that the proximity of the inorganic a-SiO2 insulation to the organic conducting channel affects considerably the magnetic response. We propose that in n-type devices, electrons in the organic conducting channel and spin bearing charged defects in the inorganic a-SiO2 insulation layer (e.g., O2 = Si+·) form oppositely charged spin pairs whose singlet-triplet spin configurations are mixed through the relatively strong hyperfine field of 29Si. By increasing the contact area between the insulation layer and the conducting channel, the ∼2% magneto-conductance response may be considerably enhanced.

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices.

A gas sensor made from graphene vertical field effect transistor (VGr-FET) has been fabricated using graphene as the source electrode, C60 thin film as the semiconductor layer and aluminum thin film as the drain electrode. The on/off ratio of transistor gated by bottom electrode with ionic liquid gel as dielectric layer is derived to be 103 from measured source–drain current Ids. The apparent energy barrier height between the graphene and polycrystalline fullerene was calculated from the model of heterojunction diode I–V response curves. The barrier height φBH was altered by the gating potential vertically applied on graphene sheet, resulting the large on/off ratio of the transistor. The effect of surface adsorption of water vapor, oxygen, ammonia and isoprene gas phase molecules on the Ids was measured. The lower limit of detection (LOD) for ammonia (86 ppb) than that of isoprene (420 ppb) is attributed to the donor nature of ammonia contact with p-type graphene, and the adsorbed donor leads to a corresponding positive gating effect to the VGr-FET. This facile, low cost and quick responsive device shows promise for early diagnose of severe human respiratory diseases.

We report a theoretical and experimental investigation of the switching characteristics in patterned-source vertical field effect transistors. Experimentally we show that the layered structure gives rise to capacitances coupling of the potential between the drain and source electrodes. By removing the extrinsic gate-source capacitance we are able to demonstrate unprecedented sub-2 μs switching and current levels of 3 A/cm2. Theoretically, using a 2D drift-diffusion model, we show that the intrinsic response depends on two processes: the formation of the virtual electrode and the injection through it to form the vertical channel. The importance of the source structure parameter to achieve ultimate speed is discussed.

Vertical field effect transistors (VFETs) using graphene and transition metal dichalcogenide (TMD) heterostructures are promising for downsizing the channel length to a monolayer TMD thickness of 0.65 nm. However, graphene/monolayer TMD/metal VFETs struggle with a low on/off ratio due to gate field screening by the graphene layer and a high off-state tunneling current caused by the large contact area. Here, we propose a 0.65 nm channel length VFET with a very high on/off current ratio made by cross-stacking top and bottom carbon nanotubes (CNTs) with a monolayer TMD in between. The ultranarrow junction area in the CNT/monolayer TMD/CNT VFET can significantly reduce the off-state tunneling current. Additionally, the gate field is transmitted from the sidewall of the bottom CNT to the monolayer MoS2 vertical channel between the two CNTs without field screening, achieving very strong gate modulation. As a result, our devices exhibit about 105 times higher on/off ratio (a maximum of 106), 105 times lower off current (10-13 A), and 560 times lower subthreshold swing (SS) (125 mV dec-1) compared to graphene/monolayer TMD/metal VFETs. In the comparison between multilayer MoS2 and monolayer MoS2 VFETs, rigid multilayer MoS2 forms a large air gap at the multilayer MoS2/CNT/substrate, which reduces electric field transmission. In contrast, monolayer MoS2 bends significantly along the sidewall of the CNT, resulting in minimal air gap formation and enhancing the electric field effect in the channel. As a result, the CNT/monolayer MoS2/CNT VFET shows a 10 times higher on-current saturation and on/off ratio compared to the CNT/multilayer MoS2/CNT VFET.

The principle of operation of Si and SiGe resistor load flip flops and Si resistor load ring oscillators of n channel vertical dual carrier field effect transistors are reviewed. Measured data from experimental verification of the principle of operation is presented.

22nm node Si SOI Coplanar “N Channel Vertical Dual Carrier Field Effect Transistors” (VDCFET) and its SOC with effective channel length less than 10nm for communication applications are presented.

Vertical low-voltage indium-tin oxide field-effect transistors (FETs) gated by microporous SiO2-based solid electrolyte are fabricated at room temperature. Our results indicate that Li ions can enhance the electric-double-layer capacitance of the microporous SiO2 solid electrolyte and reduce the operation voltage of the vertical FETs from 1.5 to 0.8 V. Such vertical low-voltage FETs exhibited a good performance with a high current output (∼1.0 A/cm2), a low subthreshold swing (<80 mV/decade), and a large on-off ratio (>106), respectively. An operation mechanism which provides a better insight into the oxide-based vertical FETs is discussed.

Two-dimensional material-based vertical field-effect transistors (VFETs) have recently garnered significant attention for their potential to enable straightforward formation of ultrashort channel lengths below a nanometer. However, their performance is often limited by unintended leakage currents arising from negative threshold voltages (Vth) and the existence of gate-field-free regions (GFFRs). To address this challenge, leakage currents through the GFFRs must be effectively suppressed under a zero gate bias. In this study, we demonstrate high-performance n-channel MoSe2 VFETs with effective leakage current suppression through GFFRs, achieving on/off current ratios exceeding 105. A vacuum pre-annealing process enables the formation of a low-defect-density MoSe2 channel with a near-zero Vth, thereby significantly reducing the leakage currents. Furthermore, the integration of high-work-function VSe2 as a drain electrode forms a defect-free van der Waals contact, suppressing the tunneling currents in the gate-modulated region. As a result, the defect-engineered MoSe2 VFET exhibited an on/off ratio that was 3 orders of magnitude higher than that of the leakage-prone MoS2 VFET. These findings provide valuable insights into charge transport mechanisms and defect-suppression strategies, laying the foundation for advancements in next-generation VFET technologies.