"Macrochip" computer systems enabled by silicon photonic interconnects

Despite significant advances in silicon photonics, optical packaging and interconnection of photonic integrated circuits constitutes a large portion of the associated manufacturing costs. Optical fibers are the dominant approach to optical interconnection. However, techniques that rely on fibers lack scalability, have low efficiency and show poor misalignment tolerance. Proposed alternative solutions using polymer waveguides have shown improved coupling efficiency, misalignment tolerance and scalability. Here we present the design, simulation and the experimental confirmation of an adiabatic silicon nitride taper to polymer waveguide coupler with only 0.52 dB of TE coupling loss at 1550-nm wavelength, excluding material loss. The coupler demonstrates $\pm 4~\mu \text{m}$ of lateral misalignment tolerance with a 1-dB penalty which, to the best of our knowledge, is the highest reported tolerance for silicon nitride to polymer waveguide coupling.

The transition from pluggable optics to co-packaged optics is having an impact on the photonic integrated circuit design automation. Traditionally, chip designers for fiber-optic systems using electronic design automation tools frequently needed a way to model a few photonic components in the same design environment with the electronics. Examples include modeling lasers or modulators with electrical driver circuits, or modeling receiver electronics with photodetector. These designs focused primarily on optimizing electronics and it was typically sufficient to model a few photonic components through electrically equivalent circuit representations using SPICE or Verilog-A. However, with the advances in silicon photonics, the photonic component count in modern PICs is rapidly growing raising serious concerns over efficacy and reliability of treating photonics as electronics. This paper describes an E-O co-design approach that (i) does not require user intervention on RF and photonic domain demarcations, and (ii) supports schematic-driven layout and back-annotation.

Today, the datacenter ecosystems are fueling the demand for novel transmitter (TX) technologies complying with the off-board, on-board, and chip-to-chip computing needs. This has set a new class of requirements for the TX infrastructure that should now offer multiple credentials, namely: high-speed, O-band operation for avoiding dispersion compensation in long distances, wavelength-division multiplexing (WDM) capabilities for higher throughput and multicasting/broadcasting support, and tight co-packaging with low-power electronics. Silicon (Si) photonic TXs have been extensively studied toward high-speed and WDM TX engines targeting mainly C-band. Only a limited number of Si-Pho O-band TXs have been reported, however with ≤32 Gb/s/channel line-rate capabilities and with a WDM portfolio that has not been fully explored yet. In this paper, we introduce a novel silicon photonic high-speed O-band TX hardware platform that can meet the current datacom and computercom interconnect requirements. We demonstrate a ring modulator (RM) based four-channel WDM TX at 4 × 40 Gb/s non-return-to-zero (NRZ) operation that supports wavelength parallelism in unicast operation but can also pave the way toward WDM TX engines for the post-100 GbE TX era. Moreover, we present a broadband Si Mach-Zehnder modulator employed in a WDM modulation scheme of 2 × 25 Gb/s NRZ signals and demonstrate multicasting when combined with a 8 × 8 passive arrayed waveguide grating router (AWGR) wavelength router, addressing the broadcasting needs of traffic usually encountered in cache-coherent multisocket settings. Finally, we further demonstrate the tight synergy of O-band Si-RM modulators with high-speed CMOS electronics, presenting an RM-based TX assembly prototype employing a fully depleted silicon-on-insulator CMOS driver, delivering 50-Gb/s NRZ operation.

In this chapter, we review the technical merits of silicon photonic devices and integrated circuits, which have benefited from high-index-contrast silicon waveguides, a high integration level of various optical functions on the same chip, and mature complementary metal-oxide semiconductor (CMOS) fabrication techniques. These technical merits assure silicon photonics as a disruptive optical technology that will achieve low-cost and compact optical modules for data communications, with applications such as chip-scale optical interconnects, short-reach communications in datacenters and supercomputers, and metro/long-haul optical transmissions. We discuss various applications in these fields, which may benefit from implementation in silicon photonics. In particular, we review silicon photonic circuits for wavelength-division multiplexing (WDM) transmitters, WDM receivers, coherent optical transmitters and coherent receivers, which all require photonic integration to reduce the cost and module size.

We are delighted to introduce a Special Issue on Optical Interconnects for the IET Optoelectronics magazine. This issue presents the current status as well as some of the outstanding progress that has been witnessed in the rapidly evolving area of optical interconnects. Today, data centres (DC) and high-performance computers are struggling with limited interconnect capacity and increased power consumption while trying to meet overwhelming bandwidth demands. As photonics technologies have been rapidly maturing, optical interconnects have come into the spotlight as the means to cope with the emerging bandwidth, energy, and capacity needs. As such, a wealth of photonic interconnect solutions across the DC hierarchy has unfolded, covering from electro-optic boards to transceiver development, on-chip and on-board switches and interconnects as well as novel noninvasive monitoring methods for light controlling for compensating thermal crosstalk, fabrication tolerances and unstable environmental conditions. At the same time, the increased penetration of optical interconnects in short-reach communications, such as board and chip levels, has triggered new challenges in photonics technologies calling for new innovations with respect to integration techniques and packaging methods. This Special Issue of IET includes integrated circuits, assembly techniques, systems-level architectures, and controlling methods related to short reach ‘chip-to-chip’, ‘in-the-box’, and ‘box-to-box’ communications. Specific areas covered by this special issue include: Silicon photonic transceiver technologies and flat DC topologies; High-speed electro-optic hosting boards and fast, energy-efficient electronics; DC switches and co-packaged optic (CPO) technologies; and Noninvasive controlling techniques for complex photonic integrated circuits. The four papers in this special section promote high-performance optical interconnect architectures and key technologies to tackle the rising bandwidth demands of DCs. They cover (a) co-packaged DC optics, (b) silicon technology transceiver modules and high-speed hosting boards for multisocket server board (MSB) interconnects and (c) automated controlling architecture for complex photonic systems; Items (b) and (c) draw from impressive achievements accomplished through the recently completed European H2020 Project ICT-STREAMS. This report written by C. Mickenberg tries to shed light on motivating factors behind co-packaged optics (CPO), the trade-offs involved and their potential impact on data centre network architectures. The article reviews the evolution of DC switch application-specific integrated circuit (ASICs) and DC optics, provides a future road map and finally discusses the potential impact of CPO on the network architecture. This topic is covered by two articles. The first, written by M. Morallis-Pegios, proposes using silicon photonics to advance interconnect throughput, socket connectivity and energy efficiency in MSB layouts by enabling a flat-topology wavelength division multiplexing (WDM) point-to-point optical MSB interconnect scheme. WDM silicon photonic transceivers coassembled with their electronic circuits achieving a 50-Gb/s line rate and 400-Gb/s aggregate data transmission are demonstrated. The article also proposes silicon photonic Arrayed Waveguide Grating Router (AWGRs) that can offer collision-less time-of-flight connectivity for up to 16 nodes. The second article covering that area is written by T. Lamprecht and reports on the development of electro-optic hosting boards for on-board transceiver subassemblies which is required to eventually form the Tb/s multi-socket onboard communication. The article also discusses the electrical interface as well as photonic board requirements, including the manufacturing technique and the assembly concept that was followed to deliver terabyte per second multichip optical communication. This article, written by F. Zanetto, introduces a novel dithering technique for real-time control of multiple cascaded photonic integrated devices, proposing a calibration-free strategy to support the development and real-life diffusion of increasingly complex photonic systems. The article elaborates on the implementation of a calibration-free automated control loop exploiting integral controllers to close a real-time feedback and stabilise the optimum working point of the employed photonic devices. The effectiveness of the proposed architectural approach is experimentally validated with the error-free routing and transmission of a 30-Gbit/s optical signal traversing a cascade of micro-ring resonator filters. All of the articles selected for this Special Issue present a wide variety of key topics and significant results addressing optical interconnects in high-performance data communication systems, including new progress on architectures, systems and packaging techniques as well as novel optimised controlling methods. As guest editors, we would like to thank all of the authors for their high-quality submissions that significantly contribute to the optical interconnect field. We would also like to thank the reviewers for their valuable and constructive technical comments that greatly enhance the Special Issue, because their feedback and comments ensure the high quality of the IET Optoelectronics Journal. We hope that this IET Special Issue will provide a useful reference of the state-of-the-art in optical interconnects to readers, and we anticipate such technological perspectives will stimulate new advancements and technological outcomes that will in turn enrich the growing field of optical interconnects. This work was supported by the E.C. through the H2020-ICT-STREAMS research project (688172).

Wavelength division multiplexing (WDM) systems are widely deployed in high-capacity long-haul transmission systems. They can provide cost-effective additional capacity on fibers overloaded by the increase in data traffic. Current WDM systems are used mainly for point-to-point transmission links. Next generation WDM technologies are expected to provide full functionality at both the system and network levels. Next generation WDM system will require many optical components, including optical filters, add/drop multiplexers, circuit switches and wavelength converters. Optical components using planar lightwave circuits (PLCs) are now widely used in WDM systems. Arrayed waveguide gratings (AWGs), in particular, play an important role in current WDM systems. In the next generation system, optical components using PLCs are expected to provide many functions that counterparts cannot. In this paper, we will describe the current and future WDM components using PLCs, focusing on AWGs and switchable add/drop filters.

In nonlinear frequency division multiplexed systems, inverse nonlinear Fourier transform (INFT) and nonlinear Fourier transform (NFT) are applied at the transmitter and receiver, respectively, so as to minimize the impact of fiber nonlinear effects. Typically, the INFT is applied at the digital signal processing of the transmitter to the individual channels of a wavelength division multiplexed (WDM) system, and these channels are linearly multiplexed using the wavelength-division multiplexer. Hence, currently, NFT-based systems suffer from nonlinear impairments due to other channels of a WDM system. This problem can be alleviated if the signals are nonlinearly multiplexed/demultiplexed using INFT and NFT in the optical domain, which is hard to achieve. In this paper, we develop a novel multistage perturbation technique to realize the NFT as the cascade of linear discrete Fourier transforms. Since all-optical discrete Fourier transforms have been implemented in silicon photonics, the proposed approach provides a promising way to implement the NFT in the optical domain. The other challenge in real time implementation of the NFT-based system is the computational complexity of the NFT. In this paper, we develop a novel nonlinear discrete Fourier transform algorithm to realize NFT. When the signal energy is small, the NFT can be evaluated by the single stage second- or third-order perturbation methods. However, as the signal energy increases, we show that the single stage technique is not accurate and the multistage perturbation technique provides reasonably accurate results for high energy signals. The number of stages required depends on the signal energy and desired accuracy. Modifying the fast Fourier transform (FFT) algorithm, the computational cost of the NFT based on the multistage perturbation technique is found to be O(KN log2 N/K), where N is the number of signal samples and K is the number of stages. An advantage of the proposed approach is that the computation can be split into FFTs of smaller lengths, which can be processed on K parallel processors. The computational cost per processor is O(N log2 N/K).

It is well known that application specific computing systems, optimally designed and configured for a given workload, offer much higher energy-efficiency and throughput than general purpose systems. In modern computing systems, heterogeneous computing systems have emerged that exploit the energy and performance benefits of combining various different domain-specific processor architectures. Application domains such as high-performance computing and machine learning now process terabyte-sized data sets, requiring enormous processing and memory resources. These applications have very high-power consumption due to bottlenecks in the electrical interconnection between processing units. This project aims to reduce both communication energy and latency by integrating universally available accelerators with silicon photonics. It also aims to increase system throughput by exploiting emerging technologies in silicon photonic reconfigurable interconnects; this will allow the system to balance itself in real time to accommodate changes in workloads and data flows.

A detailed analysis of fundamental tradeoffs between ring radius and coupling gap size is presented to draw realistic borders of the possible design space for microring resonators (MRRs). The coupling coefficient for the ring-waveguide structure is estimated based on an integration of the nonuniform gap between the ring and the waveguide. Combined with the supermode analysis of two coupled waveguides, this approach is further expanded into a closed-form equation that describes the coupling strength. This equation permits to evaluate how the distance separating a waveguide from a ring resonator, and the ring radius, affect coupling. The effect of ring radius on the bending loss of the ring is furthermore modeled based on the measurements for silicon MRRs with different radii. These compact models for coupling and loss are subsequently used to derive the main optical properties of MRRs, such as 3-dB optical bandwidth, extinction ratio of resonance, and insertion loss, hence identifying the design space. Our results indicate that the design space for add-drop filters in a wavelength division multiplexed link is currently limited to 5–10 $\mu$ m in radius and gap sizes ranging from 120 to 210 nm. The good agreement between the results from the proposed compact model for coupling and the numerical FDTD and experimental measurements indicate the application of our approach in realizing fast and efficient design space exploration of MRRs in silicon photonic interconnects.

The evaluation of the loss and the crosstalk is essential for the power budget and performance guarantee. In addition, the speed of the evaluation is important to verify different designs and proposals. However, to ensure the accuracy in the professional tools, the speed is constrained and thus not efficient for the evaluation of different designs. Thus, this work proposes a methodology of building a platform to evaluate the loss and crosstalk in silicon photonic interconnects on chip. Compared to the professional tools, the proposed methodology can offer faster evaluation results, although the evaluation accuracy is to be improved further.

We review the state of the art and our perspectives on silicon and hybrid silicon photonic devices for optical interconnects in datacenters. After a brief discussion of the key requirements for intra-datacenter optical interconnects, we propose a wavelength-division-multiplexing (WDM)-based optical interconnect for intra-datacenter applications. Following our proposed interconnects configuration, the bulk of the review emphasizes recent developments concerning on-chip hybrid silicon microlasers and WDM transmitters, and silicon photonic switch fabrics for intra-datacenters. For hybrid silicon microlasers andWDM transmitters, we outline the remaining challenges and key issues toward realizing low power consumption, direct modulation, and integration of multiwavelength microlaser arrays. For silicon photonic switch fabrics, we review various topologies and configurations of high-port-count N-by-N switch fabrics using Mach–Zehnder interferometers and microring resonators as switch elements, and discuss their prospects toward practical implementations with active reconfiguration. For the microring-based switch fabrics, we review recent developments of active stabilization schemes at the subsystem level. Last, we outline several large challenges and problems for silicon and hybrid silicon photonics to meet for intra-datacenter applications and propose potential solutions. © 2015 Chinese Laser Press.

The rapid growth in data center traffic is driving the need for increased performance and overall bandwidth of networking equipment, including optical interfaces and Ethernet switches, which are based on pluggable transceivers today. But looking just a few years ahead, bandwidth scalability challenges are looming in terms of density, cost, and power; challenges that require tighter integration of optics and networking silicon. This paper reviews the motivation for integration, the enabling technology elements, and discusses how advanced packaging and Silicon Photonics enable higher density, reduced power per bit, and ultimately the continued scalability of network bandwidth and performance.

Based on the single channel characterization of a Silicon Photonics (SiP) transceiver with Semiconductor Optical Amplifier (SOA) and semiconductor Mode-Locked Laser (MLL), we evaluate the optical power budget of a corresponding Wavelength Division Multiplexed (WDM) link in which penalties associated to multi-channel operation and the management of polarization diversity are introduced. In particular, channel cross-talk as well as Cross Gain Modulation (XGM) and Four Wave Mixing (FWM) inside the SOA are taken into account. Based on these link budget models, the technology is expected to support up to 12 multiplexed channels without channel pre-emphasis or equalization. Forward Error Correction (FEC) does not appear to be required at 14 Gbps if the SOA is maintained at 25 °C and MLL-to-SiP as well as SiP-to-SOA interface losses can be maintained below 3 dB. In semi-cooled operation with an SOA temperature below 55 °C, multi-channel operation is expected to be compatible with standard 802.3bj Reed-Solomon FEC at 14 Gbps provided interface losses are maintained below 4.5 dB. With these interface losses and some improvements to the Transmitter (Tx) and Receiver (Rx) electronics, 25 Gbps multi-channel operation is expected to be compatible with 7% overhead hard decision FEC.

We demonstrate an on-chip 0.96 TOPS hyperdimensional photonic tensor core by utilizing a time-space-wavelength multiplexed silicon photonic Crossbar (Xbar). The novel architecture relies on serializing the large matrix-vector or tensor-vector products by unfolding multiply and accumulation operations over the time domain, while simultaneously distributing the computational workload over different spatial and wavelength channels. We experimentally demonstrate the operation of a 4-channel 2-input time-space-wavelength division multiplexing (TSWDM) Xbar that incorporates 56 GHz electro-absorption modulators (EAMs) and 4-channel integrated multiplexing stages. Its successful operation as a 4×2×1 tensor-vector multiplication unit demonstrated an average relative error of 3.9%. Its performance as a photonic AI accelerator was also evaluated in the classification task of the Iris dataset, presenting experimental accuracies of 93.3% at data rates between 4×10 and 4×30 GBd, reaching 83.3% when the data rate increases to 4×60 GBd. Finally, we discuss the TSWDM Xbar scalability potential, revealing that the inclusion of a wavelength division multiplexing (WDM) scheme in the space division multiplexing (SDM) architecture reduces the operating laser power, feasibly boosting the potential of constructing photonic accelerators with computational throughput in the POPS regime.

The progressive blooming of silicon photonics technology (SiP) over the last decade has indicated that optical interconnects may substitute the electrical wires for data movement over short distances in the future. A key enabler is the resonant structures that can participate in both modulation and demultiplexing of a high throughput wavelength division multiplexed (WDM) photonic link. The optical and electro-optical properties of such devices are subject to various design considerations, operation conditions, and optimization procedures. We present recent technological advances in photonic links based on resonant structures and highlight the key challenges that must be overcome at a large scale. Furthermore, we discuss how the design space of these resonant devices, down to the geometrical parameters and fabrication errors, can affect the performance and reliability of a photonic link.