MANUFACTURING ANALYSIS OF UNDERFILL PROCESSING FOR LOW-COST FLIP CHIP ASSEMBLY

With the great environmental concern, lead-free solders gradually replace lead-based solders in electronic packages. However, the relatively short history of lead-free solders makes their reliability database inadequate. In other words, there is an urgent need to establish the reliability information of lead-free solders. In this study, a failure analysis is conducted to investigate the reliability of lead free solders. The test vehicle is the flip chip on board (FCOB) with the size of 8 mm*8 mm*0.29 mm, 0.5 mm pitch and an I/O array of 16times16 balls. The device is chosen for its recent popularity in the semiconductor packaging industry. The device includes the silicon chip, solder balls, polymeric underfill and substrate. The analysis is performed by a 3D finite element model. Both 96.5Sn/3.5Ag and 63Sn/37Pb solders are examined for their reliability by accelerated thermal cycling test (ATC) with temperatures ranging from -40degC to 150degC. This approach is used because solder joints are the weakest interconnection of the FCOB and the thermal stress induced low cycle fatigue due to mismatch in the coefficient of thermal expansion (CTE) is the key failure cause. The steady state forced convection and time- dependent elastic strain conditions are adopted. The reliability prediction is evaluated through the Kanchanomai model for 96.5Sn/3.5Ag solder balls and the Engelmaier model for 63Sn/37Pb solder balls, respectively. The simulation results indicate that the outmost solder joint has the largest Von Mises stress and strain for both lead-free and lead-based solders. The delamination between the chip and substrate is affected by the thermal-stress induced by the mismatched CTE. The reliability for lead-free solder 96.5Sn/3.5Ag can reach to 70% or above of the lead-based 63Sn/37Pb solder.

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance.

The effect of underfill material on reliability of flip chip on board (FCOB) assemblies is investigated in this study by using two-dimensional and three-dimensional finite element simulations under thermal cycling stresses from −55°C to 80°C. Accelerated testing of FCOB conducted by the authors reveals that the presence of underfill can increase the fatigue durability of solder interconnects by two orders of magnitude. Similar data has been extensively reported in the literature. It is the intent of this paper to develop a generic and fundamental predictive model that explains this trend. While empirical models have been reported by other investigators based on experimental data, the main drawback is that many of these empirical models are not truly predictive, and can not be applied to different flip chip architectures using different underfills. In the proposed model, the energy-partitioning (EP) damage model is enhanced in order to capture the underlying mechanisms so that a predictive capability can be developed. A two-dimensional finite element model is developed for stress analysis. This model accounts for underfill over regions of solder in an approximate manner by using overlay elements, and is calibrated using a three-dimensional finite element model. The model constant for the enhanced EP model is derived by fitting model predictions (combination of two-dimensional and three-dimensional model results) to experimental results for a given temperature history. The accuracy of the enhanced EP model is then verified for a different loading profile. The modeling not only reveals the influence of underfill material on solder joint durability, but also provides the acceleration factor to assess durability under life cycle environment, from accelerated test results. Experimental results are used to validate the trends predicted by the analytical model. The final goal is to define the optimum design and process parameters of the underfill material in FCOB assemblies in order to extend the fatigue endurance of the solder joints under cyclic thermal loading environments.

Flip chip on board (FCOB) technology has been in widespread application. The reliability testing of solder-joints and the delamination between underfill and chip or substrate is still a critical issue for FCOB technology. In this paper, an accelerated environmental testing HAST-was used to rapidly evaluate the reliability of area array solder bumped packages on FR-4 PCBs. The test results intend to identify the effective reliability test criteria for low-cost FCOB technology.

Flip Chip On Board (FCOB) technology, where the unpackaged silicon chip is assembled directly to an organic substrate, provides an unique interconnect structure that significantly reduces the substrate area required by traditional through hole or surface mount integrated circuit packages. Without the protection for the chip that a package body affords however, reduced mechanical robustness and a decrease in reliability performance are potential concerns. In addition, the inherent thermal mismatch between the chip and substrate, particularly with an organic printed circuit board, will produce an accumulation of stress in the solder joints under normal operating conditions that can result in relatively premature failures due to solder fatigue. Coupling the chip and substrate together with an encapsulation material under the chip face has successfully overcome these mechanical and reliability issues. However, the success of the encapsulation is dependent on many factors. Among these are the encapsulant's material properties, and the compatibility with the chip and substrate surfaces. Thus, the selection of the basic materials to be used in the FCOB assembly are interrelated and critical to achieving the desired performance from the completed assembly. This paper highlights the key considerations involved in the identification of suitable materials for each of the basic constituent elements: printed circuit board (PCB), silicon chip and encapsulation material.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The impact of underfill properties on the thermomechanical reliability of flip chip on board (FCOB) assembly is addressed in this paper. FCOB assemblies using three underfill encapsulants were subjected to a thermal cycling test. The performance of the underfill encapsulants was assessed by a statistical analysis of the failure distribution of the FCOB assemblies. The failure modes in the thermal cycling test were found to be solder joint cracks, delamination at underfill/chip passivation interface, and underfill internal cracks. An attempt was made to correlate these failures with underfill properties such as the coefficient of thermal expansion (CTE), modulus, glass transition temperature (Tg), and adhesive strength to the chip. Additionally, nonlinear finite element analysis (FEA) was conducted to verify the experimental results.

Flip chip applications typically involve solder joint interconnections between the device chip and different substrates. In most cases, the I/O's on the device chip require to be relocated to a new format such as area array in order to match the corresponding pad locations on the substrate. In this paper, we describe one implementation of the pad redistribution technology, using aluminium interconnect lines, a photosensitive polyimide insulating layer and a wettable layer of underbump metallization (UBM) for the subsequent solder bumping applications. A test vehicle employing the flip chip on board (FCOB) assembly was fabricated and subjected to the thermal cycling reliability test. A useful simulation model was applied to understand the solder joint reliability in FCOB.

Increased functionality requirements coupled with progressively reducing package size have necessitated the integration of flip chip packages into various baseband and application processor products in mobile platforms. Such products use flip chip technology using traditional capillary underfill (CUF) process on a strip based package which is subsequently over molded to finish the end-product assembly. The growing pricing pressures and competitive landscape in mobile-packaging has made it imperative for assembly subcontractors to drive the flip chip assembly cost down. To achieve this without compromising product reliability requires a fundamental shift in the way these packages are assembled. Molded underfill (MUF) approach offers such unique solution with promising advantages over CUF; such as lower material cost, higher through put and excellent reliability to meet the overall product needs of today's evolving mobile market; and is discussed in this paper. Capillary Underfill (CUF) has been the cornerstone of today's flip chip technology in both flip chip BGA and flip chip CSP format. Several advancements in CUF materials and dispense technologies made over years has made CUF the underfill technology of choice for various flip chip applications. However as the need for reducing package assembly cost has grown simultaneously; CUF material and underfill process comes under scrutiny due to higher material cost and slow through put process in the flip chip assembly flow. MUF was explored and found to be a viable lower cost alternative for mobile products by virtue of lower material cost and faster throughput due to batch process operation in strip format. The cost benefit is further complemented by the capability of MUF to enable finer spacing between die-to-die and die-to-passives; as well as smaller keep-out zones to enable reduced die-to-package edge clearance or effectively shrink the overall package size than that with CUF. Use of vacuum assisted molding was also found to be capable to fill very small gap between die and substrate of the order of 50um without voiding concerns. This paper outlines the multidisciplinary effort undertaken to design, develop, and qualify flip chip package with MUF technology for mobile application; which was successfully introduced in high volume production with yields and reliability at parity with an equivalent CUF package. MUF material with fine filler size was chosen from a material screening DOE; and was used in series of test vehicles (TVs) with different package configurations including single die and multi-die flip chip CSP packages. Process and material margin studies were conducted to establish process window for MUF technology with eutectic and Pb-free bump assemblies. Finally MUF technology was intercepted on mobile application processor product with fcTFBGA-12×12 mm sq. package and 7.5×7.5 mm2 die towards a successful introduction into high volume production. MUF challenges as well as known-limitations are also described along with future plan. Further studies are being conducted to characterize and qualify MUF on larger die sizes and/or with finer bump pitches and to establish the process and reliability margins of MUF with the same.

Following the general tendency of downsizing in microelectronic packages, the interposing layer between silicon chip and organic board is constantly reduced while the differences in thermal expansion stay constant. Consequently, thermal stresses have become the most important reliability concern in advanced packages. Finite element analysis is known as an effective way of theoretically studying the mechanical situation in multi-component systems with complex material behavior. The paper presents results of finite element simulations that provide practical guidance for design, process and material developments of chip size packaging (CSP), flip chip (FC), and direct chip attach (DCA) modules. Using realistic and efficient models, a low-cost CSP concept is assessed, the effects of underfill, underfill imperfections, and underfill defects on the reliability of FC modules are studied, and an optimum set of mechanical properties for underfill materials is proposed. Finally, reliability risk factors in DCA modules are identified and preliminary design guidelines are given.

Numerical analysis of plastic encapsulated electronic package reliability: Viscoelastic properties of underfill resin

In the last few years, flip chip technology has been increasingly employed in a variety of applications in the microelectronics industry. Comparing to conventional wirebonding technology, flip chip provides lower profile, faster signal transfer, and higher I/O density. One of the key materials used in flip chip is the underfill encapsulant, which enhances the reliability of the flip chip device by more than an order of magnitude. Currently, underfilling is carried out at the package level, e.g., each chip has to be processed individually after solder reflow. The encapsulant has to be post-cured subsequently off-line. The slow underfilling process becomes a bottleneck in the high volume manufacturing of flip chip. A joint venture program, sponsored by the Advanced Technology Program (ATP), was formed to explore the next paradigm shift in flip chip packaging technology, namely, processing underfill at the wafer level. In this process, the underfill is deposited on the wafer prior to dicing. At the assembly stage, the singulated die is processed as in standard flip chip reflow operations. The main difference is that the pre-coated underfill with built-in flux will cure concurrently with the reflow of the solder, allowing both electrical and structural interconnection to be achieved simultaneously. Therefore, this wafer level underfill process offers much potential in terms of reduced production time and increased throughput. The process will be directly suitable for high volume production using the existing assembly infrastructure, lowering the cost of implementation. In this paper, the technical challenges and the solutions for both materials development and process verification in this program will be discussed.

This paper demonstrates a combined approach of numerical analysis and experimental investigations to study the mechanical reliability of flip chip solder joints. The effect of various design parameters like bump geometry, soft and hard underfill, and used solder mask on the thermal fatigue life of solder joints is discussed. Since special attention has been directed towards Flip Chip on Board (FCOB) assemblies, constitutive properties of polymeric and solder materials are discussed in detail. The solder is modeled using a nonlinear constitutive law with time dependent (creep) and time independent plastic strains. Furthermore, material testing shows that the underfill and solder mask materials might be considered as linear viscoelastic with temperature time shift properties. Thermal mismatch between the materials assembled is often the main reason for thermally induced stresses. Thermal cycling (125/spl deg/C...-55/spl deg/C...125/spl deg/C) is therefore the load generally used in the 3D non-linear finite element analysis. Calculation results of the solder bump deformation due to temperature changes are accompanied by experimental deformation analysis. The used MicroDAC method is based on algorithms of local object tracking in images obtained from electron scanning microscopy. The measured deformation fields were utilized for proper materials selection and processing, as well as for verification of finite element analysis.

As a concept to achieve high throughput low cost flip chip on board (FCOB) assembly, a process development activity and reliability assessment is underway, implementing next generation flip chip processing based on large area underfill printing/dispensing, integrated chip placement and underfill flow, and simultaneous solder interconnect reflow and underfill cure. Reported in this work is the assembly of a series of test vehicles to evaluate the reliability of no-flow underfill materials. The reliability performance of four underfill materials is evaluated using six test vehicles. Accelerated reliability tests performed on the test vehicles included liquid/liquid and air/air thermal cycling, autoclave, and J-STD-020 Level 3 preconditioning. No-flow underfill materials tested in this work have demonstrated the ability to survive in excess of 1000 cycles of liquid/liquid thermal shock, survive more than 100 hours of autoclave, and pass J-STD-020 Level 3 preconditioning.

This paper discusses the methods of direct chip attachment (DCA) and the results of interconnect reliability qualification of flip chip assemblies with underfill. The method developed provides a 'dropin' surface mount process to attach bumped silicon devices to laminates utilizing standard surface mount assembly equipment. Assemblies of test vehicles and product modules demonstrated satisfactory results in all of the reliability qualification and product conformance criteria. Results of failure mode analysis (FMA) of assemblies subjected to thermal stress are discussed.

Fluxing underfill materials are widely used in electronics manufacturing to improve reliability performance. The prevailing process of applying fluxing underfill is by dispensing the desired volume onto the printed circuit board with optimized patterns. The underfill cure is accomplished concurrently with solder joint formation in the reflow process. Even though the processing time of applying underfill material by this method is much shorter than that of the conventional capillary flow underfill process, the processing time of underfill dispensing is much longer than other process steps (e.g., printing, chip placement, reflow, etc). The current underfill dispensing process is a bottleneck in the high-speed electronic assembly manufacturing. Besides the long processing time, the underfill dispensing process requires complicated and expensive dispensing machines, which increase the manufacturing cost. In this research, an innovative dispenseless fluxing underfill process and the associated module have been developed to achieve high-speed SMT compatible underfill processing. The underfill application and chip placement are integrated into one process step that is accomplished by one placement machine. The prototyping of flip chip on board assemblies utilizing this innovative process shows dramatically reduced processing time. It also improves the reliability of electronic assembly systems. This invention enables remarkable cost savings from shortening processing time and eliminating the capital cost associated with underfill dispensing machines. The proposed process and module are fully compatible with the current SMT electronic manufacturing infrastructure. The dispenseless underfill process provides a high-speed and cost-effective solution for flip chip, CSP, and BGA electronic packaging assembly.