Materials for Diffusion and Epitaxy

Sequential integration of thermoelectric generators (TEGs) on a silicon wafer is essential for next-generation electronics such as internet-of-things sensing network as an energy-harvesting device. A guideline of thermoelectric performance is defined as dimensionless figure of merit, zT=S2 σT/κ, which is calculated from Seebeck coefficient (S), electrical conductivity (σ), thermal conductivity (κ), and absolute temperature (T). Germanium tin (Ge1 − x Sn x ) binary alloys theoretically possess a low κ [1] and a high σ [2], implying that Ge1 − x Sn x enables high-performance TEGs. In our previous study on the thermal conductivity of Ge1 − x Sn x epitaxial layer grown on (001)-oriented Ge [3], it was revealed that a very low κ of 2.0 W/mK was obtained for a Ga-doped Ge0.929Sn0.071 epitaxial layer. The value is at least 77 and 30 times lower than that for bulk-Si (156 W/mK) and bulk-Ge (60 W/mK) [4], respectively, and same order with that for amorphous Si (1−2 W/mK) [5]. However, thermoelectric properties of the epitaxial layers could not be clarified because the underlying substrates were not electrical insulators. It is therefore, in this study, we aim to reveal thermoelectric properties of Ge1 − x Sn x epitaxial layers with a wide range of Sn contents grown by low-temperature molecular beam epitaxy. Here, semi-insulating wafers of Si, GaAs, and InP were used as a substrate in order to isolate electrically from the substrates. Combined with the results for the polycrystalline films, we will establish a guideline for enhancing the zT value in narrow band-gap group-IV materials. Acknowledgments: This work was partially supported by Grants-in-Aid for Scientific Research (S) (Grant No. 26220605) and Young Scientists (A) (Grant No. 17H04919) from JSPS in Japan and PRESTO (Grant No. JPMJPR15R2) from JST in Japan.

Silicon epitaxial growth on silicon wafers were investigated by using plasma enhanced chemical vapor deposition from SiH4/He/H2. The epitaxial layers were growm at temperatures of 350°C or lower. The base pressure of the chamber was greater than 2 × 10−5 Torr. Prior to epitaxial growth, the wafer was in-situ cleaned by H2 baking for 30 min. The epi/substrate interface and epitaxial layers were observed by cross-sectional transmission electron microscopy (XTEM). Finally, the influence of the ex-situ and in-situ cleaning processes on the qualities of the interface and epitaxial layers was discussed in detail.

Degradation of AlGaN/GaN HEMTs under elevated temperature lifetesting

Improving the quality of microelectronic devices by strained layer epitaxy

Abstract: Solar photovoltaic (PV) is a well-known energy harvesting technology or a semiconductor device that is used in generating electricity from the sunlight via the conversion process. Currently, solar photovoltaic is increasingly growing as an alternative renewable energy in conventional power generation. There are two types of solar photovoltaic cells which are monofacial and bifacial solar cells. The difference between these two solar cells is, monofacial, only generate electricity when the light touches the front side whereas the bifacial solar cell does generate electricity from both the front and rear side. In this research project, the bifacial solar cell is used to fulfil the purpose of increasing the power conversion efficiency as it can generate power from both surfaces. The bifacial is known to produce more energy up to 27 % than the monofacial according to the claims of some manufacturers. The base of this bifacial solar cell is silicon. Silicon purely contains an atomic structure that makes it suitable and more stable to be the raw material of a semiconductor due to its behaviour to block and conduct electricity. This is mainly due to silicon having the conductive properties of metal as well as an insulator. The silicon wafer will undergo the whole fabrication process to become the semiconductor devices. However, there is a problem encountered with the PV cell when it is consistently improving and when analysing the potential areas: on the power conversion efficiency. This is one of the challenges that can be solved with a strategy to increase the availability of the photon trapping of the solar cell which we called as the surface passivation of the bifacial solar cell. Surface passivation is a way that can minimise the recombination loss and efficiency loss while enhancing the optical path length of the solar cell on the photon absorption. It is the most significant step to increase the efficiency of the bifacial solar cell which is also known as an anti-reflection coating (ARC) using dye-based coating techniques. The development of the anti-reflection (ARC) lays on the fabrication techniques, optical performance and the light trapping structures as well as their impact on its efficiency

Characterization of epitaxial layers grown on 4H-SiC (0 0 0 −1) substrates

Doping can lead to residual strain and change of elastic properties in silicon. Residual strain makes silicon wafer exhibit curvature, which are used for fabricate MEMS structure. The boron doping profile is not uniform through depth, which makes doped silicon become a inhomogeneous material or Functionally Graded Material. For boron-doped circular single crystal silicon wafer, a analytical method which based on functionally graded plate mechanics theory, is proposed to calculate its curvature. Example was used to verify the analytical method through 3D finite element simulation.

With continued advances in logic devices below 10 nm design rule, the required specification for ultraclean wafer surface becomes very challenging to achieve zero defects in particles below 20 nm and lower than 0.5X1010 atoms/cm2 metal ions on the final substrate surface. Excluding crystal originated defects such as pits, stacking faults and dislocation, an ultraclean wafer surface is characterized as a surface which is particle, organic, metallic contamination, and surface roughness free. Traditional batch type RCA based wet chemical processing has been used as a major cleaning method in silicon wafer manufacturing. The biggest problem of this RCA based wet cleaning method is its side effect; a target contaminant is being removed, whereas another contaminant gets redeposited on the substrate surface. For example, APM (Ammonia Peroxide Mixture) cleaning is extremely effective in removing particle and organic contaminant, but it allows metallic contaminant to redeposit on substrate surface since the APM solution contains traces of metal ions. HPM (Hydrochloric Acid Peroxide Mixture) cleaning can remove the metal contaminant. However, it causes particle contaminant to redeposit on substrate surface because of the electrostatic attraction. The zeta potential of particles is almost positive, whereas the zeta potential of Si surface is negative in acidic solution. Since the level of a contaminant in particles and metallic concentration on the surface requires an extreme control, these side effects in conventional RCA chemistry could not be tolerated in 10 nm below device substrates. In this study, the possible chemistry modification was attempted to control both particle and metallic contaminants in DHF chemistry at final silicon wafer cleaning step. We have optimized the metal contamination procedure for Al and Cu with their analysis method with AFM by depositing nano metal particles on a silicon wafer. Al was chemically deposited on Si, whereas Cu was electrochemically deposited. Various additives such as ozone and chelating agents were chosen to add in DHF solutions to control metallic and particulate contaminants. The metal contaminants were removed by Si etching in HF and ozone mixture. The etching rate of Si increased with ozone and HF concentrations increasing. The chelating agent and HF mixture solution did not etch the silicon but oxide. The removal rates of silicon and oxide were measured in HF-based chemicals. The metal removal efficiency (MRE) has measured in various HF based solutions for Al and Cu. HF and ozone mixture was very effective in removing both metallic contaminants, but it has a certain limitation in controlling particles on silicon. The chelating agents were selected to control both metal and particles. CA 1 (chelating agent 1) and CA2 have chosen for experiments. The concentration was optimized to increase the contaminant removal efficiency. MRE higher than 95% was achieved by adding chelating agents in DHF solutions without causing a particle redeposition.

Objectives After finishing this chapter, the reader will be able to: • give two reasons why silicon is more commonly used than any other semiconductor material • list at least two preferred orientations of single-crystal silicon • list the basic steps for making silicon wafers from sand • describe the Czochralski (CZ) and the floating zone methods • explain the purpose of epitaxial silicon layer deposition • describe the epitaxial silicon deposition process • list two ways to make a silicon-on-insulator (SOI) wafer • identify the advantage of strained silicon • describe the selective epitaxial process and its application in generating strained silicon. 4.1 Introduction Single-crystal silicon wafers are the most commonly used semiconductor material in IC manufacturing. This chapter explains why silicon wafers are used the most, and how to make them. All materials are made from atoms. According to the arrangement of atoms inside solid materials, there are three different material structures: amorphous, polycrystalline, and single crystal. In an amorphous structure, there are no repeated patterns of atoms. A polycrystalline structure has some repeated patterns of atoms, which form grains. All atoms are arranged in the same repeated pattern in a single-crystal structure. Figure 4.1 shows cross sections of the three different structures. In nature, most solid materials are either amorphous or polycrystalline in structure. Only a few solids have a single-crystal structure, and they are usually gem stones, such as quartz (single-crystal silicon dioxide), ruby (single-crystal aluminum oxide with the presence of the element chromium), sapphire (single-crystal aluminum oxide with different impurities other than chromium), and diamond (single-crystal carbon).

Summary form only given. A full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material process has been developed that meets the following criteria: (1) the material quality is identical to epitaxial silicon layers; (2) the SOI layer thickness is well controlled; (3) the insulator material choice and thickness is variable; (4) the device-to-device isolation is left to customer discretion. In the FELT/SOI process, a p+ etchstop layer is fabricated on a lightly doped starting substrate followed by epitaxial layer deposition with the type and resistivity required for the final SOI layer. Next an insulator layer is either grown or deposited followed by thick polysilicon deposition as is typical in standard DI process. The original substrate is now mechanically ground up to the vicinity of p+ etchstop layer. The remaining silicon overlying the etchstop layer and the etchstop layer itself are then removed in doping sensitive etches followed by surface finish. The SOI layer thickness control over a nominally 10- mu m layer on a 4-in wafer is +or-0.5 mu m, and the layer shows no material defects. Bipolar transistors fabricated on this material and epitaxial control material show comparable performance in terms of high gain sharp junction breakdown, and good yield. >

Addressing the systematic errors introduced by dual-beam interference models in epitaxial layer thickness calculations and considering the robustness of actual interference phenomena, this study establishes a calculation model for the relationship between reflectance and epitaxial layer thickness under multi-beam interference conditions. This research is significant for improving the accuracy and reliability of thickness measurement in semiconductor manufacturing processes, which is a critical parameter for controlling device performance and yield. First, the necessary conditions for multi-beam interference are deduced, including identical frequencies, consistent vibration directions, constant phase differences, light source characteristics, and low absorption rates of the medium. Their impact on thickness calculation accuracy is analyzed, concluding that higher precision amplifies noise effects. The model innovatively incorporates the Airy formula, combining it with the Fresnel equations and the Zeilemann dispersion formula to derive an analytical expression for total reflectance. By applying nonlinear least squares fitting to experimental spectral data from silicon wafers, an optimal thickness of 30.0312 μm was obtained with a relative deviation of only 0.02%, indicating negligible error consistent with practical conditions. Simultaneously, fitting data from silicon carbide epitaxial layer attachments using this precise model yielded a thickness of 8.0192μm, partially eliminating systematic errors introduced by simplified models.

InGaAs strained epitaxial layers on GaAs are of considerable interest in semiconductor devices. An important feature is the critical thickness of the epitaxial layer beyond which relaxation occurs, affecting the device performance. With this in view, a series of such structures have been grown by organometallic vapor phase epitaxy and characterized by ion channeling, high resolution x-ray diffraction and Raman spectroscopy. The results of these three techniques are compared for the samples in this study which are fully strained, nominally and by experimental measurements. Beam steering effect that occurs at low energy channeling is also addressed.

Liquid phase epitaxy of GaAs and AlGaAs

As a promising way to scale down semiconductor devices, 193-nm immersion exposure lithography is being developed at a rapid pace and is nearing application to mass production. This technology allows the design of projection lens with higher numerical aperture (NA) by filling the space between the projection lens and the silicon wafer with a liquid (de-ionized water). However, direct contact between the resist film and water during exposure creates a number of process risks. There are still many unresolved issues and many problems to be solved concerning defects that arise in 193-nm immersion lithography. The use of de-ionized water during the exposure process in 193-nm immersion lithography can lead to a variety of problems. For example, the trapping of microscopic air bubbles can degrade resolution, and residual water droplets left on the wafer surface after immersion exposure can affect resolution in the regions under those droplets. It has also been reported that the immersion of resist film in de-ionized water during exposure can cause moisture to penetrate the resist film and dissolve resist components, and that immersion can affect critical dimensions as well as generate defects. The use of a top coat is viewed as one possible way to prevent adverse effects from the immersion of resist in water, but it has been reported that the same problems may occur even with a top coat and that additional problems may be generated, such as the creation of development residues due to the mixing of top coat and resist. To make 193-nm immersion lithography technology practical for mass production, it is essential that the above defect problems be solved. Importance must be attached to understanding the conditions that give rise to residual defects and their transference in the steps between lithography and the etching/cleaning processes. In this paper, we use 193-nm immersion lithography equipment to examine the transference (traceability) of defects that appear in actual device manufacturing. It will be shown that defect transfer to the etching process can be significantly reduced by the appropriate use of defect-reduction techniques.

В работе приводится технология изготовления полупроводниковых приборов c повышенной радиационной стойкостью. Тонкопленочные транзисторы из а-Si могут быть созданы в виде различных структур: испарением металлического электрода шириной 30 мкм и методом PECVD из смеси SiH4 и NH3 осаждением тонкого диэлектрического слоя SiHx . На этот слой осаждается слой a-Si:H толщиной 0,3 мкм методом разложения SiH4 в тлеющем разряде. Технология разработки состоит в следующем: на кремниевых пластинах после создания тонкого затворного оксида по стандартной технологии поверх нее над канальной областью формируют слой нитрида кремния Si3N4 толщиной 40–80 нм при расходе газовой смеси SiH4 –N2 35–40 см3 /мин в реакторе, давлении газовой смеси 0,4 мм рт. ст., ВЧ-мощности 100 Вт, концентрации силана в смеси 1 мол%, температуре подложки 400°С и скорости осаждения нитрида кремния Si3 N4 0,3 нм/с. Нанесение слоя нитрида кремния поверх слоя оксида улучшает рабочие характеристики полупроводниковых приборов и повышается радиационная стойкость. The paper presents a technology for producing semiconductor devices with increased radiation resistance. Thin-film transistors made of a-Si can be created in the form of various structures: by evaporation of a 30 μm wide metal electrode and by the PECVD method from a mixture of SiH4 and NH3 by deposition of a thin dielectric layer of SiHx . A 0.3 μm thick a-Si:H layer is deposited on this layer by the method of decomposition of SiH4 in a glow discharge. The development technology is as follows: after creating a thin gate oxide on silicon wafers using standard technology, a 40–80 nm thick layer of silicon nitride Si3 N4 is formed on top of it above the channel region at a flow rate of 35–40 cm3 /min of the SiH4 –N2 gas mixture in the reactor, a gas mixture pressure of 0.4 mm Hg. Art., RF power of 100 W, silane concentration in the mixture of 1 mol%, substrate temperature of 400°C and deposition rate of silicon nitride Si3N4 of 0.3 nm/s. Deposition of a layer of silicon nitride over the oxide layer improves the performance characteristics of semiconductor devices and increases radiation resistance.