MECP

The diffusion space of data diffusion architectures

In the big data era, a huge number of services has placed a fast-growing demand on the capacity of DRAM-based main memory. However, due to the high hardware cost and serious leakage power/energy consumption, the growth rate of DRAM capacity cannot meet the increased rate of the required main memory space when the energy or hardware cost is a critical concern. To tackle this issue, hybrid main-memory devices/modules have been proposed to replace the pure DRAM main memory with a hybrid main memory module that provides a large main memory space by integrating a small-sized DRAM and a large-sized non-volatile memory (NVM) into the same memory module. Although NVMs have high-density and low-cost features, they suffer from the low read/write performance and low endurance issue, compared to DRAM. Thus, inside the hybrid main-memory module, it also includes a memory management design to use DRAM as the cache of NVMs to enhance its performance and lifetime. However, it also introduces new design challenges in both the OS and the memory module. In this work, we rethink the interactivity of OS and hybrid main-memory module, and propose a cross-layer cache design that (1) utilizes the information from the operating system to optimize the hit ratio of the DRAM cache inside the memory module, and (2) takes advantage of the bulk-size (or block-based) read/write feature of NVM to minimize the time overhead on the data movement between DRAM and NVM. At the same time, this cross-layer cache design is very lightweight and only introduces limited runtime management overheads. A series of experiments was conducted to evaluate the effectiveness of the proposed cross-layer cache design. The results show that the proposed design could improve access performance for up to 88%, compared to the investigated well-known page replacement algorithms.

Incorporating load factor into the scheduling of soft real-time transactions for main memory databases

This paper analyzes the trade-offs in architecting stacked DRAM either as part of main memory or as a hardware-managed cache. Using stacked DRAM as part of main memory increases the effective capacity, but obtaining high performance from such a system requires Operating System (OS) support to migrate data at a page-granularity. Using stacked DRAM as a hardware cache has the advantages of being transparent to the OS and perform data management at a line-granularity but suffers from reduced main memory capacity. This is because the stacked DRAM cache is not part of the memory address space. Ideally, we want the stacked DRAM to contribute towards capacity of main memory, and still maintain the hardware-based fine-granularity of a cache. We propose CAMEO, a hardware-based Cache-like Memory Organization that not only makes stacked DRAM visible as part of the memory address space but also exploits data locality on a fine-grained basis. CAMEO retains recently accessed data lines in stacked DRAM and swaps out the victim line to off chip memory. Since CAMEO can change the physical location of a line dynamically, we propose a low overhead Line Location Table (LLT) that tracks the physical location of all data lines. We also propose an accurate Line Location Predictor (LLP) to avoid the serialization of the LLT look-up and memory access. We evaluate a system that has 4GB stacked memory and 12GB off-chip memory. Using stacked DRAM as a cache improves performance by 50%, using as part of main memory improves performance by 33%, whereas CAMEO improves performance by 78%. Our proposed design is very close to an idealized memory system that uses the 4GB stacked DRAM as a hardware-managed cache and also increases the main memory capacity by an additional 4GB.

Suffix trees for inputs larger than main memory

Middleware implementation of various critical services required by large scale and complex real time applications on top of COTS operating system is currently an approach of growing interests. Its main goal is to enable significant reduction application system design separating the concerns of the application designer for the application functionality from the concerns for application independent system issues. The paper presents the middleware architecture named the Real-time Object-oriented Adaptive Fault Tolerance Support (ROAFTS) and a prototype implementation ROAFTS/Solaris realized on top of both a COTS operating systems, Solaris, and a COTS CORBA complaint ORB, Orbix. ROAFTS supports distributed real time applications, each structured as a network of Time-triggered Message-triggered Objects (TMOs), and the TMO is a major extension of a conventional object for use in hard real time applications. The major components of ROAFTS include a TMO support manager for supporting the execution of TMO's, a generic fault tolerance server, and a network surveillance manager (NSM) which provides the generic fault tolerance server with fast fault detection notices. The generic fault tolerance server and the NSM themselves have been structured as TMO's. A discussion on an effective use of CORBA standards for moderate precision real time applications to run on COTS operating systems is also presented.

In this paper, an online heuristic is proposed and evaluated, for managing the dynamic memory in a computer system with active disks, by physically colocating in disk memory or main memory, the data pages being accessed by a computation slice. This enables a runtime system that can offload the corresponding computation slice to the appropriate processing unit at the disk memory or main memory. A modified version of SEQUITUR, an online compression algorithm, is used to identify the affinity among sets of pages in a virtual memory page reference stream, and a page allocation and replacement policy is presented. The sets of pages identified are shown to closely match the sets of pages referenced by computation slices, using a suite of data access kernels as benchmarks. The paging policy is evaluated with page traces of micro benchmarks and real applications. In memory constrained environments, with additional memory at the disk, most of the benchmarks see improved performance, due to fewer page faults. The paging heuristic can colocate 50% of the affinity sets on average and can offload up to 100% of the computation to disk.

A strongly connected component (SCC) is a maximal subgraph of a directed graph G in which every pair of nodes are reachable from each other in the SCC. With such a property, a general directed graph can be represented by a directed acyclic graph DAG by contracting an SCC of G to a node in DAG. In many real applications that need graph pattern matching, topological sorting, or reachability query processing, the best way to deal with a general directed graph is to deal with its DAG representation. Therefore, finding all SCCs in a directed graph G is a critical operation. The existing in-memory algorithms based on depth first search (DFS) can find all SCCs in linear time w.r.t. the size of a graph. However, when a graph cannot resident entirely in the main memory, the existing external or semi-external algorithms to find all SCCs have limitation to achieve high I/O efficiency. In this paper, we study new I/O efficient semi-external algorithms to find all SCCs for a massive directed graph G that cannot reside in main memory entirely. To overcome the deficiency of the existing DFS based semi-external algorithm that heavily relies on a total order, we explore a weak order based on which we investigate new algorithms. We propose a new two phase algorithm, namely, tree construction and tree search. In the tree construction phase, a spanning tree of G can be constructed in bounded sequential scans of G. In the tree search phase, it needs to sequentially scan the graph once to find all SCCs. In addition, we propose a new single phase algorithm, which combines the tree construction and tree search phases into a single phase, with three new optimization techniques. They are early acceptance, early rejection, and batch processing. By the single phase algorithm with the new optimization techniques, we can significantly reduce the number of I/Os and CPU cost. We conduct extensive experimental studies using 4 real datasets including a massive real dataset, and several synthetic datasets to confirm the I/O efficiency of our approaches.

Caching is an important technique to improve computer system performance by storing the most recently used data and instructions for main memory. Cache is widely used in modern computer systems and will continue to be an irreplaceable unit to narrow the speed gap between processor and main memory. With the increasing capacity of main memory and the number of processor cores, the cache technology has great development. In this paper, we have some lessons of cache hierarchy changes with the memory technology from experimental methodology. We design a serial of experiments and try to answer some questions about cache designs. Our experiments results indicate that more levels of cache does not necessarily means better performance for all benchmarks, that last level cache miss rate has no direct connection with the system performance, that the average performance of exclusive cache hierarchy is more effective than that of inclusive cache.

The declining cost of main memory and need for high performance database systems have recently inspired research into systems with massive amounts of memory and the ability to store complete databases in main memory It is recognized that in this framework the issues concerned with efficient database recovery are more complex than in traditional DBMS systems. In this paper we define a classification method for main memory database (MMDB) recovery techniques and discuss the results of a performance analysis conducted examining the different classes.

Main memory virtualization is used to expand the effective main memory capacity meaning that more virtual main memory is represented to guest operating systems than physical memory is actually available. This is done by compressing and uncompressing memory pages. Obviously the price for main memory virtualization is a higher CPU utilization, especially when dealing with high workloads. SAP ERP systems represent the backbone of today's enterprises and have a very high resource demand. The combination of main memory virtualization and SAP ERP system is of great importance but has not yet been thoroughly researched. This paper is the first approach to a quantitative research for evaluating the performance impact of memory virtualization on SAP ERP systems. We utilize a synthetic main memory benchmark, called Zachmanntest, to evaluate the performance impact of main memory virtualization on a SAP ERP system. As an exemplary main memory virtualization implementation IBM's Active Memory Expansion is used, where a so called expansion factor can be used to specify the size of the virtual main memory. Performance results show that the greater the expansion factor, the greater the performance impact. Regarding the peak performance, throughput of SAP ERP systems may be decreased till -17%, whereas the overall throughput of such systems may experience a decrease up to -42% when dealing with a very high compression factor.

In this paper, the adaptive cancellation structure is first developed based on the LMS algorithm and FIR adaptive filtering. Then the novel practical noise and echo cancellation systems are built using the proposed adaptive technique and implemented using TX320TMS67C13 DSKs, which are Texas Instruments’ Digital Signal Processing (TI DSP) boards. Although adaptive filtering is an exciting topic in which many real-life applications can be explored [1]-[6], [9], building such a real-time system is often challenging due to the use of theoretical math, advanced DSP knowledge and practical industrial hands-on experience [1],[4]-[6],[9]. Therefore, this paper indicates that it is possible to apply traditional mathematics in adaptive filtering theory to real-time practical DSP systems. With the MATLAB software tool, we can simulate and verify various adaptive filtering designs first. Then, development and implementation of different noise or echo cancellation systems with adaptive filtering techniques can be successfully performed using the floating-point digital signal processor, TX320TMS67C13 DSK. Furthermore, it can be shown that TX320TMS67C13 DSKs with their stereo channels offer more effective and flexible tools for various noise cancellation applications.

Distributed real-time systems have continually being developed for many real applications. It is very important to assure the reliability of such systems. However, developing a fault-free distributed real-time system is very difficult. Duplication is one of the fault-tolerant technologies for improving the reliability of distributed real-time computer systems. In this paper, we present a dual-cluster distributed real-time system model with four states to improve the reliability of distributed real-time systems. The system employs cluster switch, output arbitration and fault detection to increase its reliability. The system's availability is evaluated according to the model. We also introduce a dynamic approach for visualizing and debugging the timing behavior of distributed real-time systems.

Nowadays, Wireless Mesh Networks (WMN) are increasingly supporting jointly non real-time and real time applications that required a guaranteed bandwidth. A new methodology is presented throughout this study to show that an important aspect of dimensioning WMNs, considering mobility of users, fairness and their demand according to two types of running applications. This leads to satisfying voice demand while ensuring fairness among the non delay-sensitive applications. We propose the combination of both capacity estimation based on users mobility and multipath scheme. We compare our proposition with single path routing based on the shortest path criteria in terms of end-to-end throughput to show that it performs best.

The GNSS time transfer technology is the high precision time transfer method based on the navigation satellite system and has been widely applied in time and frequency. Benefiting from the development of GNSS time transfer technology and the expansion of user needs for real-time time service applications, real-time time transfer technology has become an important research direction. GNSS Precise Point Positioning (PPP) is one of the most commonly used methods of GNSS time transfer technology. With the development of the many facilities, the application of the real-time GNSS PPP has become wider and wider. In this paper, we demonstrate and evaluate the performance of the international GNSS service (IGS) products in the near real-time PPP time transfer technology. A set of the PPP solutions were computed from the observed data from the timekeeping laboratories, and three types of products provided by IGS, including Ultra-Rapid (IGU), Rapid (IGR), and Final (IGS final) orbit and clock offset products. IGS final and IGR products have extremely high accuracy and stability and are used as a reference for the time transfer with IGU product. The near real time clock offset and the comparison link performed with the IGU product can provide a time comparison service with an accuracy of 0. 5ns for near real time applications.