Memory management scheme for cost-effective disk-on-modules in consumer electronics devices

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

Nand flash memory, which has shock-resistant, less noise, and high I/O operations per second (IOPS) compared with Hard Disk Drive (HDD), has been widely used in various fields such as mobile, PC, server system. Despite of its advantages, NAND flash memory has erase-before-write characteristic which needs to be handled by Flash translation layer (FTL). Thus, NAND flash memory performance depends on the FTL design itself. Exsiting FTL studies mostly focused on improving FTL algorithm and further improve NAND flash memory performance. However, there are not enough studies that exploits multi-core processors which become popular nowadays. In this paper, we proposed a new multi-thread FTL which uses the advantage of multi-core processors.

NAND flash memory has long been the dominant storage medium in mobile devices. However, power failure may occur at any time and result in loss of important data. Crash recovery therefore becomes vitally important in NAND flash memory storage systems. As flash translation layer (FTL) directly manages flash memory using various metadata, the problem of FTL crash recovery in NAND flash is how to efficiently and effectively maintain and recover the consistency of FTL metadata after system crash.In this paper, we present DCR, a deterministic approach to crash recovery for NAND flash based storage systems. The basic idea is to exploit the determinism of FTL and reproduce events that happened between the last checkpoint and the crash point during crash recovery. Different from existing approaches which have to scan the whole flash memory chip, we show that DCR can recover the system more efficiently by only checking a limited number of blocks based on deterministic FTL operations. We have implemented DCR for a block-level FTL and compared it with a popular version-based scheme using an ARM11-based embedded evaluation board. Experimental results show that DCR can greatly reduce recovery time and guarantee the consistency of FTL metadata after recovery.

MaCACH: An adaptive cache-aware hybrid FTL mapping scheme using feedback control for efficient page-mapped space management

Recent consumer devices such as smartphones, smart TVs and tablet PCs adopt NAND flash memory as storage device due to its advantages of small size, reliability, low power consumption, and high performance. The unique characteristics of NAND flash memory require an additional software layer, called flash translation layer (FTL), between traditional file systems and flash memory. In order to reduce the garbage collection cost, FTLs generally try to separate hot and cold data. Previous hot and cold separation techniques monitor the storage access patterns within storage device, or exploit file system hints from host system. This paper proposes a novel clustered page-level mapping, called CPM, which can separate hot and cold data efficiently by allocating different flash memory block groups to different logical address regions. CPM can reduce the FTL map loading overhead during garbage collection and it does not require any high-cost monitoring overhead or host hint. This paper also proposes a K-associative version of CPM, called K-CPM, which allows different logical address regions to share a physical block group in order to achieve high block utilizations. Experimental results show that CPM improves the storage I/O performance by about 54% compared with a previous page-level mapping FTL, and K-CPM further improves the performance by about 19.4% compared with CPM.

Flash translation layer (FTL) is a firmware embedded in NAND-based block devices. It hides unique characteristics of NAND flash memory and emulates a standard block device interface. The overall performance of NAND-based block devices is mainly determined by the efficiency of the FTL schemes, and thus, it is important to evaluate the FTL performance to design high-speed NAND-based block devices, which is a main objective of this work. Whereas most previous works have not considered device utilization from a FTL perspective and have fixed the over-provisioning factor, this work evaluates their performance varying device utilization and allows unused space to be used as over-provision area. A trace-driven simulation shows that device utilization significantly influences on FTL’s performance. Especially, the page mapping FTL is vulnerable against high utilization, even though it delivers a good performance at low utilization. In contrast, the fully associative sector translation (FAST) FTL is less sensitive to the utilization and delivers a competing performance. It even outperforms the page mapping FTL at high utilization.

Flash memory has been widely used in various embedded computing systems and portable devices in recent years because of its small size, shock-resistance, low-power consumption and non-volatile properties. To hide the disadvantages of flash memory such as out-of-place update, a flash translation layer (FTL) is usually used for providing transparent block-device emulation. But when index structures are implemented over FTL, intensive overwrite operations caused by record inserting, deleting, modifying and index reorganizing could not only degrade the performance significantly but also reduce the life of flash memory. To address the problem, BFTL and IBSF are proposed. However, neither of them could avoid the loss of records and incompatibilities when system crash occurs. In this paper, a reliable B-tree implementation called RBFTL is presented for flash-memory storage systems. It is placed between the application layer and FTL. RBFTL could minimize the loss of data and eliminate incompatibilities effectively and efficiently when system crashes. The experimental results also show that RBFTL yields a better performance than FTL.

In NAND flash-based storage systems, an intermediate software layer called a Flash Translation Layer (FTL) is usually employed to hide the erase-before-write characteristics of NAND flash memory. We propose a novel superblock-based FTL scheme, which combines a set of adjacent logical blocks into a superblock. In the proposed Superblock FTL, superblocks are mapped at coarse granularity, while pages inside the superblock are mapped freely at fine granularity to any location in several physical blocks. To reduce extra storage and flash memory operations, the fine-grain mapping information is stored in the spare area of NAND flash memory. This hybrid address translation scheme has the flexibility provided by fine-grain address translation, while reducing the memory overhead to the level of coarse-grain address translation. Our experimental results show that the proposed FTL scheme significantly outperforms previous block-mapped FTL schemes with roughly the same memory overhead.

A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk

Flash storage devices behave quite differently from hard disk drives (HDDs); a page on flash has to be erased before it can be rewritten, and the erasure has to be performed on a block which consists of a large number of contiguous pages. It is also important to distribute writes evenly among flash blocks to avoid premature wearing. To achieve interoperability with existing blockI/O subsystems for HDDs, NAND flash devices employ an intermediate software layer, called the flash translation layer (FTL), which hides these differences. Unfortunately, FTL implementations require powerful processors with a large amount of DRAM in flash controllers and also incur many unnecessary I/O operations which degrade flash storage performance and lifetime. In this paper, we present a refactored design of I/O architecture for flash storage which dramatically increases storage performance and lifetime while decreasing the cost of the flash controller. In comparison with page-level FTL, our preliminary experiments show a reduction of 19 percent in I/O operations, improvement of I/O performance by 9 percent and storage lifetime by 36 percent. In addition, our scheme uses only <inline-formula><tex-math>$\frac{1}{128}$</tex-math></inline-formula> DRAM memory in the flash controller.

NAND flash memories have been widely adopted as storage on computing devices, since it has strong effectiveness on performance. However, asymmetric operation performance of NAND flash memories still impedes high performance. To mitigate this performance hurdle, most storage devices of NAND flash memories have used Flash Translation Layer (FTL). In this paper, we propose a novel workload-aware FTL mapping policy, called Multi-level Associated Sector Translation (MAST). MAST divides log block depending on characteristics of data, and dynamically detects hot pages to avoid unnecessary merge operations of FTL. In experimental results, we show that our approach outperforms FAST method by 10% and LAST by 3%, respectively.

NAND flash memory has been widely used to build embedded devices such as smartphones and solid state drives (SSD) because of its high performance, low power consumption, great shock resistance and small form factor. However, its lifetime and performance are greatly constrained by partial page updates, which will lead to early depletion of free pages and frequent garbage collections. On the one hand, partial page updates are prevalent as a large portion of I/O does not modify file contents drastically. On the other hand, general-purpose cache usually does not specifically consider and eliminate duplicated contents, despite its popularity.In this paper, we propose a hybrid approach called FTL2, which employs both logging and mapping techniques in flash translation layer (FTL), to tackle the endurance problem and performance degradation caused by partial page updates in flash memory. FTL2 logs the latest contents in a high-speed temporary storage, called Content Cache to handle partial page updates. Experimental results show that FTL2 can greatly reduce page writes and postpone garbage collections with a small overhead.

FTL (Flash Translation Layer) is a memory block controller that manages the challenges of a data storage system based on flash memory technology. The design of internal parallelism in MLC-based SSDs with virtual blocks resulted in various challenges and due to the physical structure of flash memory cells based on MLC technology, it is possible to write a new page in a data block at the address after the last page is written. In parallel-based SSD design based on virtual blocks, some writes create unusable pages at the memory space, and these created holes reduce memory efficiency; consequently, it reduces the life-time of memory blocks by creating more operations, and accelerates garbage collection and merging operations. The proposed FTL offers three steps to address this constraint. Firstly, an idea was proposed to prevent costly transitions and to distribute data more evenly at memory blocks (wear leveling). Secondly, the unused holes created in virtual blocks became much fewer resulting in increased utilization of memory space. At last, a policy was proposed to prevent update blocks (log blocks) from being blocked and to postpone the merging and garbage collection by which the memory lifetime increases significantly. Simulation results showed that the number of unused erased pages and the number of extra write operations decreased up to 23% and 17%, respectively. In addition, the number of invalid released pages increased up to 21% in the proposed FTL, and the speed of I/O executions to 3%.

Flash memory is being rapidly deployed as data storage for embedded devices such as PDAs, MP3 players, mobile phones and digital cameras due to its low electronic power, non-volatile storage, high performance, physical stability and portability. The most prominent characteristic of flash memory is that prewritten data can only be dynamically updated via the time consuming erase operation. Furthermore, every block in flash memory has a limited program/erase cycle. In order to manage these issues, the flash memory controller can be integrated with a software module called the flash translation layer (FTL). This paper surveys the state-of-art FTL algorithms. The FTL algorithms can be classified by the complexity of the algorithms: basic and advance. Furthermore, they can be classified by their corresponding tasks: performance enhancement and durability enhancement. The FTL algorithms corresponding to each classification are further broken down into various schemes depending on the methods they adopt. This paper also provides the information of hardware features of flash memory for FTL programmers.

ZTL: A block layer ZNS driver