Memory optimization of bilateral filter and its hardware implementation

This paper presents an area and power-efficient architecture for serial commutator real-valued fast Fourier transform (FFT) using recursive look-up table (LUT). FFT computation consists of butterfly operations and twiddles factor multiplications. The area and power performance of FFT architectures are mainly limited by the multipliers. To address this, a new multiplier is proposed which stores the partial products in LUT. Moreover, by adding the shifted version of twiddle coefficients, the stored partial products gain symmetry, and thus the size of LUT can be reduced to half. Further symmetry is achieved by adding another shifted version of twiddle coefficients and so on. This makes the proposed LUT multiplier recursive in nature. A new data management scheme is suggested for the proposed architecture. To validate the proposed architecture, application-specific integrated circuit (ASIC) synthesis and field-programmable gate array (FPGA) implementation are carried out for different symmetry factor. For instance, the proposed architecture for 1024-point with symmetry factor of two achieves 39.11% less area, 42.29% less power, 33.27% less sliced LUT (SLUT) and 29.18% less flip-flop (FF) as compared to the best existing design.

In this paper, we present an efficient look-up table (LUT)-based approach to design multipliers for GF(2 m ) generated by irreducible trinomials. A straightforward LUT-based multiplication requires a table of size (m×2 m ) bits for the Galois field of degree m. The LUT size, therefore, becomes quite large for the fields of large degrees recommended by the National Institute of Standards and Technology (NIST). Keeping that in view, we have proposed a digit-serial LUT-based design, where operand bits are grouped into digits of fixed width, and multiplication is performed in serial/parallel manner. We restrict the digit size to 4 to store only 16 words in the LUT to have lower area-delay complexity. We have also proposed a digit-parallel LUT-based design for high-speed applications, using the same LUT as the digit-serial design, at the cost of some additional multiplexors and combinational logic for parallel modular reductions and additions. We have presented a simple circuit for the initialization of LUT content, which can be used to update the LUT in three cycles whenever required. The proposed digit-serial design involves less area-complexity and less time-complexity than those of the existing LUT-based designs. The proposed digit-parallel design offers nearly 28 % improvement in area-delay product over the best of the existing LUT-based designs. NIST has recommended five binary finite fields for elliptic curve cryptography, out of which two are generated by the trinomials Q(x)=x 233+x 74+1 and Q(x)=x 409+x 87+1. In this paper, we have designed a reconfigurable multiplier that can be used for both these fields. The proposed reconfigurable multiplier is shown to have a negligible reconfiguration overhead and would be useful for cryptographic applications.

This study presents the detailed design and analysis of a new memristor-based look-up table (LUT) for field programmable gate arrays (FPGAs). The proposed memory utilises memristors as storage elements with N-type metal-oxide-semiconductor transistors for row access. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation. The proposed method requires a RESTORE pulse only for the READ 0 operation. Moreover, the WRITE operation of the proposed method requires three power lines and a RESTORE pulse only for the READ 0 operation, thus saving 25% READ time when compared with previous methods. In addition, the proposed method does not require the REFRESH pulse and does not dissipate power during stand-by mode. Extensive simulation results are presented with respect to different operational features such as normalised state parameter, pulse width and LUT size. In addition to a circuit-level evaluation, the proposed LUT scheme has also been assessed with respect to FPGA implementation. Simulation results using sequential benchmarks mapped on Spartan 4 and 5 FPGAs show that the proposed non-volatile LUT outperforms existing static random access memory cell-based LUTs in terms of performance.

While the development of the optic interferometric sensors achieves great progress, one fact that restricts this development is the demodulation technique. An applicable demodulation method for interferometric sensors is called "The Phase Generated Carrier (PGC) demodulation". Yet this demodulation fails to content the large-scale sensors application for the limitations of the electronic devices. Another arctangent approach based on digital demodulator proves more advantages than the traditional Differentiate and Cross Multiply (DCM) approach which is used in PGC demodulation. In this paper, the arctangent approach based on PGC demodulation is discussed and simulated. Lookup table is used in the arctangent approach. Values equal to the existent data in the lookup table are chosen from the table, and values between two different data in the table are modulated to the linear approximate values. Two primary objects are aimed to demonstrate the advantages of the arctangent approach: (1). the noise analysis of this demodulation, considered two aspects: a. the relativity of the noise amplitude and the size of lookup table. Simulation result indicates that when double the lookup size, the noise amplitude decreases about 6dB; b. the influence to the noise generation which is leaded in by the rank of the polynomial approximate coefficients, the higher this rank is, the better the result comes. An approximate function is proposed about this relationship. (2). the measurement range, operation complexity, quality of operation, and applicability of the arctangent approach are discussed for an effective digital realization.

Computing with memory, which stores function responses of some input patterns into lookup tables offline and retrieves their values when encountering similar patterns (instead of performing online calculation), is a promising energy-efficient computing technique. No doubt to say, with a given lookup table size, the efficiency of this technique depends on which function responses are stored and how they are organized. In this paper, we propose a novel adaptive approximate lookup table based accelerator, wherein we store function responses in a hierarchical manner with increasing fine-grained granularity and accuracy. In addition, the proposed accelerator provides lightweight compensation on output results at different precision levels according to input patterns and output quality requirements. Moreover, our accelerator conducts adaptive lookup table search by exploiting input locality. Experimental results on various computation kernels show significant energy savings of the proposed accelerator over prior solutions.

In the C-band high-speed long-reach optical intensity modulation direct detection (IM/DD) communication system, severe signal distortion, including chromatic dispersion and device bandwidth limitations, making the size of lookup tables (LUTs) required by equalizers too large to be operated. In this paper, we propose a cluster-assisting lookup table (CLUT) approach to reduce the table size significantly. In addition, we also propose multiplication-free CLUT-based decision-feedback equalizer (CLUT-DFE) and CLUT-based log-maximum a posteriori estimation with a fixed number of surviving states (CLUT-FS-MAP) to effectively compensate for channel distortions. Using the k-means clustering algorithm, the proposed CLUT significantly shortens the table size by reducing the number of independent variable values input. The table size of traditional LUTs increases exponentially with the filter tap number, making it impossible for LUTs to replace filters with tap numbers greater than 20. The CLUT breaks this limitation. The proposed schemes are experimentally performed in a C-band 61-Gb/s IM/DD optical on-off keying (OOK) system featuring a 3.65-GHz 3-dB bandwidth over a 100-km standard single mode fiber (SSMF). Compared to traditional LUT, CLUT reduces table size by about 10 orders of magnitude with the same performance. To the best of our knowledge, this study represents the first deployment of ultrasmall-size CLUT in equalization.

This report presents results on the development of an adaptive predistorter for a generic TDMA transmitter A heterodyne architecture was used with the quadrature modulator and demodulator implemented as digital circuits. Previously reported results have indicated that increasing the look-up table (LUT) size improves the ACPR. Our results showed an opposite trend. Typical adjacent channel power rejection (ACPR) values of -57 dB were achieved using a 16 point LUT. The small LUT size may be attributed to memory effects inherent in a heterodyne system.

Clustering of Medical Images for Analysis: A Fuzzy Approach

A digital pre-distortion (DPD) scheme based on an adaptive-memory-length look-up table (AML-LUT) is proposed and experimentally demonstrated in a four-level pulse amplitude modulation (4-PAM) underwater optical wireless communication (UOWC) system. By implementing adaptive memory length for each pattern in the AML-LUT-based DPD, the size of the AML-LUT can be significantly reduced without sacrificing performance compared to both the full-size LUT and the multi-symbol simplified look-up table (MSS-LUT)-based DPDs. The performance of the proposed AML-LUT-based DPD is experimentally evaluated for a 625 Mbit/s 4-PAM UOWC over 1 m transmission length. Experimental results show that compared with the full-size LUT with a memory length of 7 (LUT-7)-based DPD, the proposed AML-LUT-based DPD (i) incurs a marginal power penalty of 0.5 dB at both the 7% hard-decision forward error correction (HD-FEC) and KP4-FEC threshold limits, while simultaneously reducing the implementation complexity (i.e., the LUT size) by 93%; (ii) achieves comparable transmission performance compared to the MSS-LUT-based DPD, while reducing the implementation complexity by 89%; and (iii) shows great potential for high-speed, low-complexity and memory-efficient intensity modulation and direct detection (IM/DD) UOWC and short-reach optical interconnects.

A memory and speed efficient CAVLC (context adaptive variable length coding) decoder for H.264/AVC baseline profile is proposed. Because the CAVLC consists of a kind of bit-level operations, general processor (like RISC or MIPS) and DSP incorporating multiple parallel arithmetic units (like SIMD or VLIW) are ineffective to decode it. Though the dedicated hardwires are very effective to decode the CAVLC, they are expensive and not programmable. Also, the size of the CAVLC lookup table is more than 400 bytes. Demand for highly flexible and fast implementations and lower memory size for CAVLC decoding is rising nowadays. The four instructions--ShowBits, GetBits, FlushBits and LeadingBits, are designed after the exploiting of the functions coverage. In order to reduce the codewords matching miss and the lookup table size, a new grouping, remainder generation method and a merged lookup table (LUT) are used; and the specific group decoding instruction GroupDecoding is also presented. In summary, a based instruction set level acceleration with the codewords group partition hardware architecture is proposed to speed up the CAVLC decoding. Based on those instructions and the hardware platform, the CAVLC decoding can be significantly accelerated compared with the method in H.264 reference software. Simulation results show that the architecture is sufficient for the CAVLC decoding of 30 frames HDTV (1902 x 1080 pixels) per second.

Guided image filtering is one of the widely used techniques in computer vision. However, it commonly leads to over‐smoothed edges and a distorted appearance when tackling intricate texture patterns and complex noise. In this paper, a window‐aware image filtering framework based on the bilateral filter guided by the local entropy is presented. The key idea of the authors' proposed approach is to design a novel guidance input and a non‐box filtering window. Specifically, using the Gaussian spatial kernel and the local entropy, a GEF that can maintain image feature details and yield a robust guidance input for BF is constructed. Meanwhile, based on an intensity‐similar strategy, the local non‐box filtering window is designed for the further preservation of edge structures. The authors' approach not only inherits the advantages of bilateral filter i.e. simplicity, parallelisation and easiness of programming, but also is more powerful than bilateral filter and its variants. In addition, the guided entropy filter and the non‐box window can also be transplanted to other local filters and can effectively improve the filtering effects. The qualitative and quantitative experimental results demonstrate that the authors' approach has good performance in image denoising, texture (or background) smoothing, edge extraction and other applications in image processing.

Bilateral filtering (BLF) and median filtering (MF) are key components in many applications. As the image resolution grows rapidly, implementation of efficient filtering is highly demanded. In this paper, we present a unified VLSI architecture that is able to compute both kinds of filters for 4k2k videos at 30fps. One feature of this design is that we leverage an emerging layer-based algorithm for both BLF and MF, which turns the non-linear BLF or MF into a set of linear filtering followed by output interpolation. It allows more accurate approximation than previous works. Moreover, to address the introduced design challenges of filter units and comparison units, we propose an architecture with moving sum method (MSM) of box filtering and a parallel component selector (PCS), respectively. The MSM requires only one line buffer, and the PCS architecture allows us to complete the comparison in one cycle. Furthermore, a shared pre-computation unit is also proposed to support both kinds of filters. As a result, our design costs only 6.33KB on-chip memory and 161.5K logic gates to support both BLF and MF. It is much efficient than existing architectures which support BLF only.

Recently, we have proposed the antisymmetric product coding (APC) and odd-multiple-storage (OMS) techniques for lookup-table (LUT) design for memory-based multipliers to be used in digital signal processing applications. Each of these techniques results in the reduction of the LUT size by a factor of two. In this brief, we present a different form of APC and a modified OMS scheme, in order to combine them for efficient memory-based multiplication. The proposed combined approach provides a reduction in LUT size to one-fourth of the conventional LUT. We have also suggested a simple technique for selective sign reversal to be used in the proposed design. It is shown that the proposed LUT design for small input sizes can be used for efficient implementation of high-precision multiplication by input operand decomposition. It is found that the proposed LUT-based multiplier involves comparable area and time complexity for a word size of 8 bits, but for higher word sizes, it involves significantly less area and less multiplication time than the canonical-signed-digit (CSD)-based multipliers. For 16- and 32-bit word sizes, respectively, it offers more than 30% and 50% of saving in area-delay product over the corresponding CSD multipliers.

The computation capacity of conventional FPGAs is directly proportional to the size and expressive power of Look Up Table (LUT) resources. Individual LUT performance is limited by transistor switching time and power dissipation, defined by the CMOS fabrication process. In this paper we propose OLUT, an optical core implementation of LUT, which has the potential for low latency and low power computation. In addition, the use of Wavelength Division Multiplexing (WDM) allows parallel computation, which can further increase computation capacity. Preliminary experimental results demonstrate the potential for optically assisted on-chip computation.

In this paper, a novel and area-efficient variable length decoder (VLD) for MPEG-1/2/4 is presented. Instead of carrying out every variable length coding table with one dedicated lookup table (LUT) directly, we employ an efficient clustering-merging technique to reduce both the size of a single LUT and the total number of LUTs required for MPEG-1/2/4. Synthesis results show that our VLD occupies 10666 gate counts and operates at 125 MHz by using the standard cell from Artisan TSMC's 0.18 mum process. As demonstrated, the proposed design outperforms other VLDs with less hardware cost. It can decode a symbol of different standards in every cycle and support video resolution of HD1080 at 30 frames/s for MPEG-1/2/4 real-time decoding.