MEMS deep-RIE fabrication process and device characterization

In this work, a silicon-based micro-probe array was fabricated using multi-step deep reactive ion etching (DRIE) and reactive ion etching (RIE) processes. The micro-probe structure was implemented using a micromachining technique through a combination of two anisotropic DRIE and two isotropic RIE processes with a single etch mask. The cone-shaped tip height and tapered tip-end angle were experimentally varied with respect to the first DRIE depth. As the first DRIE depth was decreased, the micro-probe tip height increased and the sharpness consequently improved. The conductive layer was exposed only at the tip ends of the micro-probe to form a conical ultra-micro electrode, and it was characterised via cyclic voltammetry measurements.

Switchable wetting and flexible SiC thin film with nanostructures for microfluidic surface-enhanced Raman scattering sensors

This paper reports an advanced deep reactive ion etching (DRIE) process for realizing ultra-deep ( 500-μm) and ultra-high aspect-ratio (UHAR) silicon structures (AR 40 for 1-mm through-trench etch, AR ≈ 80 for 500-μm through-trench etch, and AR 20 for 500-μm through-hole etch), with straight sidewalls across a wide range of feature sizes. The challenges of making such structures are overcome by continuously ramping critical parameters of the Bosch DRIE process throughout the process, including the 380-kHz bias power during etch step, the etch/passivation step duration, and the chamber pressure. The masking material capable of enduring the long DRIE process is also discussed; 10-μm and 25-μm wide trenches are etched to a depth of 750-μm and 1000-μm, respectively, in 1-mm-thick silicon wafers with straight sidewall profiles and flat trench bottoms. Deeper trenches are expected to be etched beyond a 1-mm thick wafer with thicker and/or higher selectivity masking materials. We have also demonstrated etching of circular holes of diameters as small as 25-μm to a depth of 500-μm, and potentially with 10-15 μm diameter holes. This advanced DRIE process offers opportunities for applications ranging from through-silicon via in 3-D CMOS integration to emerging microand meso-scale microelectromechanical system applications that demand ultra-deep and UHAR DRIE.

The thickness of a capacitive disk resonator can be increased by selecting a deep reactive ion etching (DRIE) process for reducing motional resistance. However, the DRIE process sometimes causes MEMS capacitive resonators to have a non-ideal profile. In this paper, the slope effect of a resonator profile fabricated by a DRIE process on the capacitance, electrostatic force, electrical stiffness, motional resistance and output current of the capacitive resonator is analyzed. The relation curves between these parameters and the sloped angle are obtained theoretically. The results show that the capacitance, electrostatic force, electrical stiffness and output current decrease as the sloped angle increases, but the motional resistance obviously increases. By capturing the electric field distribution of a capacitive resonator with different ratios of the gap to thickness by using FEM software ANSYS, the effects of slope angle and thickness on the natural frequency of the resonator are investigated. The analyzed results can provide the theoretical basis for designing high-performance MEMS disk resonators fabricated by the DRIE process.

The increasing need for functionality and portability in consumer electronics is pushing the microelectronics industry to develop more effective interconnection techniques. This has resulted in the birth of 3D stacking of chips, which is achieved by the use of TSV (Through-Silicon-Via) technology. This paper puts forward a TSV simulator, FASTsv (Fast and Accurate Simulator of TSV: FASTsv). The key technologies in TSV process include DRIE (deep reactive ion etching) and PECVD (plasma-enhanced chemical vapor deposition) processes. Based on experimental results and theoretical analysis, the modeling of DRIE and PECVD processes are developed. Experimental tests are performed to verify the TSV simulator. The simulation results agree with experimental results very well.

Recently, demands for nanochannels have been increasing in biological and nanofluidic applications. In this paper, a fabrication process that produces a nanochannel with a width of less than 20 nm and a high aspect ratio is proposed. For the versatility of channel pattern design, focused ion beam (FIB) direct writing is applied for mask fabrication. A metal mask pattern is fabricated using localized ion implantation method and is used for a deep reactive ion etching (DRIE) process. A process condition for minimum undercut in the DRIE process is determined. The proposed method is applied to the fabrication of nanochannels with various dimension and patterns.

Development, fabrication, and test of a modular eddy current micro sensor on a flexible polymer foil

Hierarchical nanostructures are typically fabricated with multiple lithography steps on prepatterned micro- or nanostructures. However, such conventional multiple lithography steps result in poor coverage and uniformity, especially when patterning on high-aspect-ratio micro- or nanostructures. In this work, the authors present a new fabrication method which can make hierarchical nanostructures even on high-aspect-ratio prepatterns, using a free-standing trilayer membrane. The nanoporous trilayer composite films, consisting of metal/photoresist/antireflective coating, is created on a planar silicon substrate by using laser interference lithography, reactive ion etching, and e-beam deposition. Then, a customized solution of ammonia (NH3), hydrogen peroxide (H2O2), and water (H2O) is used to release the composite film from the supporting substrate. The free-standing composite membrane is then transferred on a prepatterned silicon substrate. Showing no major defects on the membrane surface, the flexible and soft trilayer membrane allows a good, uniform contact with the top surface of the prepatterns and is utilized as a robust etch mask in the deep reactive ion etching (DRIE) process of silicon to fabricate hierarchical nanopore structures. Since the membrane covers the top surfaces of the prepatterns seamlessly, the nanopore patterns of the membrane are transferred onto the top surfaces with great fidelity during the etching process. The membrane can also be used as a stencil for deposition processes. For example, metal is deposited through the nanoporous membrane by a lift-off process. Then, the transferred metal nanodot patterns are used as an etch mask in the DRIE process to achieve high-aspect-ratio hierarchical nanopillar structures. Compared to conventional methods to fabricate hierarchical nanostructure, the introduced new approach is more reliable and versatile to realize large-area hierarchical nanostructures with a good uniformity, in both nanopore and nanopillar array by using the same single membrane.

We are developing novel ultra light-weight and high-resolution X-ray micro pore optics for space X-ray telescopes. In our method, curvilinear micro pore structures are firstly fabricated by silicon deep reactive ion etching (DRIE) or X-ray LIGA processes. Secondly, side walls of the micro structures are smoothed by magnetic field assisted finishing and/or hydrogen annealing techniques for high reflectivity mirrors. Thirdly, to focus parallel X-ray lights from astronomical objects, these structures are elastically or plastically bent into a spherical shape. Fourthly, the bent structures are stacked to form a multi-stage X-ray telescope. In this paper, we report on fabrication and X-ray reflection tests of silicon and nickel X-ray mirrors using the DRIE and LIGA processes, respectively. For the first time, X-ray reflections were confirmed on both of the mirrors. Estimated rms roughnesses were 5 nm and 3 nm for the silicon and nickel mirrors, respectively.

Semiconductor technology is a new technology that has only begun to develop in recent decades, but after just a few decades of development, it has become one of the largest industries in the world today, and it exists in many products in our daily lives. In the last few years, the demand for semiconductors surged, even in automobiles, computers and other industries. Due to the shortage of semiconductor chips, a chain shortage effects are caused in many other fields. Therefore, advanced semiconductor technology is very urgent. In semiconductor technology, etching technology accounts for about one-third of the total process capital cost and a large amount of time cost. The reactive ion etching and deep reactive ion etching in this paper are the most advanced techs among all etching technologies today. This paper first explained the mechanisms of the two technologies, and analyzed etching performance with various influencing factors.

An advanced reactive ion etching process for very high aspect-ratio sub-micron wide trenches in silicon

Deep reactive-ion etching (DRIE) is commonly used for high aspect ratio silicon micromachining. However, scalloping, which is the result of the alternating Bosch process of DRIE, can cause many problems in the subsequent process and degrade device performance. In this work, we propose a simple and effective method to smoothen the scalloping of DRIE trenches. The proposed method utilizes sidewall dry etching by reactive-ion etching (RIE) based sulfur hexafluoride (SF6) plasmas, following the DRIE process. To investigate the effect of the etch parameter on the scallop smoothing effect, the radio frequency (RF) power and gas flow are controlled. After the RIE treatment, the scallop smoothing effects were evaluated by measuring the average scallop depth under each condition. The scallop depth was reduced by 91% after implementing the scallop smoothing technique using RIE. Thus, our smoothening method based on SF6 plasmas would provide broad availabilities and applicability in silicon micromachining with the simple low-temperature process.

A simple, low‐cost and reliable dicing‐free silicon‐on‐insulator (SOI) process is presented for solving three major challenges in manufacturing the microelectromechanical systems devices, i.e. stiction, notching and dicing damage. In this process, the cavity is used and patterned on the handle layer to solve the stiction problem, and the exposed oxide is removed in hydrofluoric acid (HF) solution before deep reactive ion etching (DRIE) on the structure layer to eliminate the notching effect's impact. The dies are attached temporally to a designed frame by the silicon dioxide. After removing the oxide using HF solution, the dies are separated from the wafer cleanly without dicing damage. The layout design rules on the front side and backside patterns are established. Furthermore, a grooved carrier wafer with specific design rules was introduced to enhance the yield rate of the process. Finally, a tuning fork gyroscope was fabricated to demonstrate the proposed fabrication process and a yield rate of over 81% was achieved. The process solves the stiction, notching and dicing damage problems only involving the apparatus associated with lithography and DRIE, offering an economic and complete SOI process solution.

A novel micro-electromechanical system (MEMS) technology-based grating laser scanner with a backside thinned grating platform has been successfully developed for high-speed laser scanning applications. The grating platform is thinned by a round cavity and reinforced by a circular frame, which are fabricated using a single mask delay etching (SMDE) technique. The SMDE technique, which utilizes the well-know loading effects of the deep reactive ion etching (DRIE) process, is a simple and low-cost methodology to regulate the etching rate of a prescribed area. It can be used in a silicon-on-insulator (SOI) micromachining process to form multilevel structures in a silicon device layer through a multi-step DRIE process from a wafer's backside. This paper presents the design, simulation, fabrication process and characterization of the high-speed MEMS grating scanner as well as the principle and applications of the SMDE technique. When illuminated with a 635 nm wavelength incident laser beam, the prototype scanner with a 1 mm diameter diffraction grating is capable of scanning at 50.192 kHz with an optical scan angle of 14.1°.

Surface wettability in terms of the size of the micro nano structures has been examined. To evaluate the influence of the nano structures on the contact angles, we fabricated two different kinds of structures: squarepillar-type microstructure with nano-protrusions and without nano-protrusions. Microstructure and nanostructure arrays were fabricated by deep reactive ion etching (DRIE) and reactive ion etching (RIE) processes, respectively. And plasma polymerized fluorocarbon (PPFC) was finally deposited onto the fabricated structures. Average value of the measured contact angles from microstructures with nanoprotrusions was 6.37° higher than that from microstructures without nano-protrusions. This result indicates that the nano-protrusions give a crucial effect to increase the contact angle.