Method and apparatus for compacting integrated circuits with standard cell architectures

Integrated circuit (IC) layout designs must conform to formalized and non-formalized constraints. These constraints are often embedded in physical design software in the form of design rule checking. IC layout designs are verified through the help of design rule checking (DRC), layout vs. schematic (LVS), and manual inspection courtesy of the design engineer. However, manually inspecting every layout design for errors is slow and impractical. This problem has led to the proposal of utilizing a combination of machine learning, deep learning, and computer vision methods to verify the integrity of IC layout designs. The goal of this study is to present a methodology to automatically detect and classify IC transistor layout errors. A color-based feature characterization technique was used to extract the features from IC layout images. In addition, machine learning models for multioutput-multiclass classification were explored to classify errors on IC layouts. Classification metrics such as macro average, precision, recall, and F1-score were used to evaluate the performance of the proposed system. As a result, random forest obtained 99.75% on classifying error types while multilayer perceptron obtained 92.26% on classifying error sub-categories of transistor-level integrated circuit layouts.

The number of guillotine partitions in d dimensions

A Passivated Emitter and Rear Contact Cell (PERC) defines a new architecture of solar cell which differs from standard cell architecture. PERC enhances light capture at the rear surface and to optimize electron capture. This leads to an increase (or) achieve better efficiency than when compared with standard cell which are reaching their physical limits. In this paper, the characterization of bifacial p-type PERC solar cell with various proportions of tallness and width, back Silicon Nitrate layer with various thickness are streamlined. Most elevated back productivity of the bifacial solar cell (~22%) was obtained at AM 1.5 (air mass), 1000 W/m2, 26 °C standard test condition.KeywordsPERCBifacialFingerGeneration profileReflectionAbsorbtion

A new method of packing the rectangles is proposed with applications to integrated circuit (IC) layout design. A special work-sheet, called the bounded-sliceline grid, is introduced. It consists of special segments that dissect the plane into rooms to which binary relations "right-of" and "above" are associated such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of the modules into the rooms followed by a compaction procedure. Changing the assignments by swapping the contents of two rooms, a simulated annealing strategy is implemented to search for a good packing. Empirical results show that hundreds of rectangles are packed with a quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Ideas to handle a multilayer, nonrectangular chips with L-shaped modules are suggested.

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.

In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM® CortexTM-A5 processor using a 65nm library, and shows up to 38% reduction in area cost when compared to traditional voltage area layout.

In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.

The effective resistance of a resistive mesh is a commonly used analogy for various scientific and engineering problems such as voltage drop estimation, distributed control including time synchronization and sensor localization, determining the chemical distance among multiple bonds, and finding the distance between two vertices in a graph. Resistive networks are a commonly used structure in electronics to model different elements of an integrated circuit, such as a physical substrate, an integrated circuit layout, and a power distribution network. On-chip power and ground networks are composed of orthogonal metal lines from different metal layers, and a resistive mesh is typically used to model these networks. A two layer mesh is therefore commonly used to analyze IR voltage drops and decoupling capacitor placement. A closed-form expression is described here for the effective resistance between the intersections of a two layer resistive mesh where the horizontal and vertical unit resistances are different. The physical distance between the nodes of interest and the ratio between the horizontal and vertical resistances are included in the expression. The maximum error of the closed-form expression, as compared with the exact solution, is less than 5% for a wide range of . The error further decreases with greater separation between the nodes of interest.

Power Integrated Circuit (IC) needs to consume huge currents so it often includes a large size device. In order to approach IC driving capabilities, 1.5 times to the simulation size can be used. In this study, 40 % reduction in IC layout can be reached after the correct simulation tool flow is adopted.

A multi-scale modeling approach is proposed and employed to investigate thermal issues and to enable "thermally aware" design of radio-frequency (RF) integrated circuits (ICs). Thermal analysis from full-chip scale down to the single transistor level was made possible with the development of this approach using the finite volume three-dimensional (3D) numerical technique. We have developed new tools that import GDSII layout of entire IC and, for the purpose of generating full-chip 3D thermal model, automatically eliminate the minuscule layout elements that do not affect thermal results. We present here our approach and examples of using equivalent thermal conductivity blocks in place of "forest of vias" typical in modern ICs. Our method and tools are demonstrated on a couple of RF ICs based on a high performance SiGe BiCMOS technology. The tool provides a 3D temperature map that can show thermal gradients across a chip, as well as local temperature distribution (hot spots) down to single transistor level. This allows introducing temperature back into design process. The multi-scale modeling is verified with infrared temperature measurements.

Standard cell libraries are an important part of many of today's integrated circuit (IC) designs. The design of all digital ASICs (Application Specific Integrated Circuit) essentially involves the use of an ASIC standard cell library comprising logic functional primitives such as basic gate functions, complex combinational functions, sequential elements, arithmetic elements and 1I0s. In this paper the work involves, designing standard cell layouts with different cells using fixed height of standard cell template and characterizing standard cells using liberate and generating. lib file for standard cell. This Standard cell library was designed an industry academia chip collaborative project. By using Cadence virtuoso, liberate tools high performance with low power consumption standard cell library was developed.

Surface plasmon lithography (SPL) overcomes the diffraction limit of conventional projection lithography by utilizing evanescent waves for imaging, offering significant potential for integrated circuit (IC) manufacturing at advanced technology nodes. Previous research on the imaging quality in SPL has primarily focused on enhancing the resolution of imaging structures, neglecting the compatibility with diverse mask patterns. Given the diversity and complexity of patterns in IC layouts, exploring imaging structures compatible with varied mask patterns is essential. This paper focuses on the robustness of superlens imaging structures, introducing the concept of a robust imaging structure. It also establishes a flow for robustness optimization and analyzes imaging quality and compatibility using the coherent transfer function (CTF). This study examines the influences of polymethylmethacrylate (PMMA) and photoresist (Pr) thicknesses on imaging quality, as well as the impact of the top Ag thickness turning point on imaging quality. Simulation experiments and analytical demonstrations reveal that robust imaging structures exhibit higher amplitude and broader high-amplitude bandwidth in the spatial frequencies of evanescent waves, resulting in improved compatibility. This study aims to guide the optimization of imaging structures in practical applications of surface plasmon lithography. The proposed method is suitable for robustness optimization of imaging structures for diverse mask patterns at advanced technology nodes.

The paper reports on design decisions taken in the modelling, design and implementation of a full set of SPARC v8 Integer Unit versions and gives data about the experimental results obtained. VHDL was the description language, Synopsys tools were for the logical synthesis, and Duet Technologies' Epoch was used for the physical layout of the final circuits. These have been carried out in a 0.35 /spl mu/m, three-metal layer CMOS process. The description strategy and the design flow methodology allow us to obtain quantitative results that characterize suitable points in the design space. They show how much microarchitecture, design, datapath granularity and module decisions affect performance and cost functions. This design space exploration down to physical layouts is made possible by modelling techniques based on configurable VHDL descriptions.

This paper presents the methods we used to achieve an exhaustive comparison of specific arithmetic operators and the result of this comparative study. The operators we were interested in are modular adders that can be used for Residue Number System (RNS) processors. RNS arithmetic provides an alternative way to produce highly effective multiplication and addition and are, therefore, of great interest for signal processing processors. As modular adders are at the root of any RNS processor, attention must be payed to their design. We expose three different existing designs for such adders and through the construction and use of generators that produce 0.35μ standard cell architectures, we synthesized those three designs for all odd moduli from 4 to 15 bits and measured their performance. Performance was measured after placement and routing of those operators providing precise results. The exhaustive data obtained let us compare those three designs based on size, speed or any combination of those two fore-mentioned factors. Eventually this study gives clues on choosing a specific modular adder for a given modulus and also for choosing the best candidates for a well balanced residue base (i.e. choosing a good set of moduli). Furthermore, it shows that the described parallel modular adder is generally the best choice.

The book all semiconductor device engineers must read to gain a practical feel for latchup-induced failure to produce lower-cost and higher-density chips. Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process. Presents real cases and solutions that occur in commercial CMOS IC chips Equips engineers with the skills to conserve chip layout area and decrease time-to-market Written by experts with real-world experience in circuit design and failure analysis Distilled from numerous courses taught by the authors in IC design houses worldwide The only book to introduce TLU under system-level ESD and EFT tests This book is essential for practicing engineers involved in IC design, IC design management, system and application design, reliability, and failure analysis. Undergraduate and postgraduate students, specializing in CMOS circuit design and layout, will find this book to be a valuable introduction to real-world industry problems and a key reference during the course of their careers.