Optimizing Power IC Layouts by Simulation Tools

The number of transistors per chip, feature sizes, frequencies, transistor densities, number of cores, thermal design powers, die areas, and storage capacities of Integrated Circuits (ICs) used for different processing units and memories were collected from various websites from 1973 to 2019 and plotted against year of introduction of ICs in semi-log paper to find the trend with R-squared (R2) value using Microsoft Excel. The R2 values of the trend lines for the above parameters were over 0.922 which indicated that more than 92% of data satisfied the fitting lines except for thermal design power (R2 = 0.7) and die area (R2 = 0.4 to 0.6). It was observed that the growths of transistor counts, transistor densities, frequencies, and thermal design powers for different processing units were growing exponentially and doubled every 16.8 to 24 months from 1973 to 2019 except the growth of thermal design powers (TDP) and frequencies of ICs which were increased up to 2003. After that, the growth of TDP and frequencies are nearly linear up to the present day. The growth of the above parameters for ICs of different memories was a little faster, it was doubled every 14 to 16 months. The feature sizes shrunk 2 times every 18 months. A strong relation was found between feature sizes and transistor densities (R2 = 0.9) and observed that one fold of feature size decreased for the increasing of 2-3 folds of transistor densities. It was observed that different parameters for ICs designing from 1973 to 2019 kept pace with Moore's law. It may be concluded that the decrease of feature size, increasing of transistor count and transistor density in ICs design will follow Moore's law for some more years with the limitation of frequency and power of ICs.

Integrated circuit (IC) layout designs must conform to formalized and non-formalized constraints. These constraints are often embedded in physical design software in the form of design rule checking. IC layout designs are verified through the help of design rule checking (DRC), layout vs. schematic (LVS), and manual inspection courtesy of the design engineer. However, manually inspecting every layout design for errors is slow and impractical. This problem has led to the proposal of utilizing a combination of machine learning, deep learning, and computer vision methods to verify the integrity of IC layout designs. The goal of this study is to present a methodology to automatically detect and classify IC transistor layout errors. A color-based feature characterization technique was used to extract the features from IC layout images. In addition, machine learning models for multioutput-multiclass classification were explored to classify errors on IC layouts. Classification metrics such as macro average, precision, recall, and F1-score were used to evaluate the performance of the proposed system. As a result, random forest obtained 99.75% on classifying error types while multilayer perceptron obtained 92.26% on classifying error sub-categories of transistor-level integrated circuit layouts.

Method and apparatus for compacting integrated circuits with standard cell architectures

A monolithic GaN power integrated circuit (IC) with power devices, logic, drive, and protection circuits is a candidate system for a future low power consumption power IC. Formation of a high quality GaN MOS interface is a key for realizing the GaN Power IC. Although a good interface property of a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /GaN structure have already reported[1], the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /GaN structure has obvious interfacial Ga-oxide layer. On the other hand, we have established to form a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /GaN interface without an obvious interfacial layer and with a low interface trap density (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">It</sub> )[2]. However, carrier conduction in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /GaN structure with the abrupt interface has not yet been investigated. In this study, characteristics of current density (J) vs oxide field (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> ) in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers formed by the remote-oxygen- plasma enhanced CVD (ROPE-CVD) on a GaN surface were investigated through comparisons of J-E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> characteristics between GaN and Si MOS capacitors.

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.

To decrease the switching loss and the dead-time effect of resonant half-bridge inverter, a novel adaptive dead-time control circuit of resonant half-bridge driver Integrated Circuit (IC) is presented. Without increasing the pin number of IC, this circuit takes a novel strategy to adaptively regulate dead time to a temperate range between high and low thresholds. The high and low thresholds are adaptive to the fall time of output signal in a half-bridge clock cycle. The IC of the designed circuit is suitable for high-voltage applications. The dead-time regulation range of this circuit achieves 0–3.5 µs. The range of temperate dead-time state is 300 ns. The failure signal of this circuit can protect the IC and peripheral power devices by regulating operation in three clock cycles. Both simulation and measurement of the proposed circuit in a half-bridge driver IC with an operating frequency at 50 kHz are presented based on the 0.5 µm 700 V BCD process. The results of simulation and measurement show that the presented circuits’ performance is perfect.

In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.

The number of guillotine partitions in d dimensions

A multi-scale modeling approach is proposed and employed to investigate thermal issues and to enable "thermally aware" design of radio-frequency (RF) integrated circuits (ICs). Thermal analysis from full-chip scale down to the single transistor level was made possible with the development of this approach using the finite volume three-dimensional (3D) numerical technique. We have developed new tools that import GDSII layout of entire IC and, for the purpose of generating full-chip 3D thermal model, automatically eliminate the minuscule layout elements that do not affect thermal results. We present here our approach and examples of using equivalent thermal conductivity blocks in place of "forest of vias" typical in modern ICs. Our method and tools are demonstrated on a couple of RF ICs based on a high performance SiGe BiCMOS technology. The tool provides a 3D temperature map that can show thermal gradients across a chip, as well as local temperature distribution (hot spots) down to single transistor level. This allows introducing temperature back into design process. The multi-scale modeling is verified with infrared temperature measurements.

The concept of cut-and-paste customization is introduced for the first time in designing integrated circuits based on mechanically flexible organic field-effect transistors, and is applied to electronic artificial skin. The electronic artificial skin comprise of three separate integrated circuits that are a pressure-sensor array, row decoders, and column selectors to read out pressure information over a large area. All of three integrated circuits are scalable in size because the pressure-sensor array is a simple repetition of sensor cells and the row and column decoders adopt wired-NAND circuits, which enables the cut-and-paste customization in size. The physical cut-and-paste procedure is employed by cutting a part of the integrated circuits and pasting it to another integrated circuit with a connecting plastic tape. The integrated circuits are designed with a standard SPICE simulator and layout design tool, and the operation is confirmed by measurement.

The effective resistance of a resistive mesh is a commonly used analogy for various scientific and engineering problems such as voltage drop estimation, distributed control including time synchronization and sensor localization, determining the chemical distance among multiple bonds, and finding the distance between two vertices in a graph. Resistive networks are a commonly used structure in electronics to model different elements of an integrated circuit, such as a physical substrate, an integrated circuit layout, and a power distribution network. On-chip power and ground networks are composed of orthogonal metal lines from different metal layers, and a resistive mesh is typically used to model these networks. A two layer mesh is therefore commonly used to analyze IR voltage drops and decoupling capacitor placement. A closed-form expression is described here for the effective resistance between the intersections of a two layer resistive mesh where the horizontal and vertical unit resistances are different. The physical distance between the nodes of interest and the ratio between the horizontal and vertical resistances are included in the expression. The maximum error of the closed-form expression, as compared with the exact solution, is less than 5% for a wide range of . The error further decreases with greater separation between the nodes of interest.

Surface plasmon lithography (SPL) overcomes the diffraction limit of conventional projection lithography by utilizing evanescent waves for imaging, offering significant potential for integrated circuit (IC) manufacturing at advanced technology nodes. Previous research on the imaging quality in SPL has primarily focused on enhancing the resolution of imaging structures, neglecting the compatibility with diverse mask patterns. Given the diversity and complexity of patterns in IC layouts, exploring imaging structures compatible with varied mask patterns is essential. This paper focuses on the robustness of superlens imaging structures, introducing the concept of a robust imaging structure. It also establishes a flow for robustness optimization and analyzes imaging quality and compatibility using the coherent transfer function (CTF). This study examines the influences of polymethylmethacrylate (PMMA) and photoresist (Pr) thicknesses on imaging quality, as well as the impact of the top Ag thickness turning point on imaging quality. Simulation experiments and analytical demonstrations reveal that robust imaging structures exhibit higher amplitude and broader high-amplitude bandwidth in the spatial frequencies of evanescent waves, resulting in improved compatibility. This study aims to guide the optimization of imaging structures in practical applications of surface plasmon lithography. The proposed method is suitable for robustness optimization of imaging structures for diverse mask patterns at advanced technology nodes.

A new method of packing the rectangles is proposed with applications to integrated circuit (IC) layout design. A special work-sheet, called the bounded-sliceline grid, is introduced. It consists of special segments that dissect the plane into rooms to which binary relations "right-of" and "above" are associated such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of the modules into the rooms followed by a compaction procedure. Changing the assignments by swapping the contents of two rooms, a simulated annealing strategy is implemented to search for a good packing. Empirical results show that hundreds of rectangles are packed with a quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Ideas to handle a multilayer, nonrectangular chips with L-shaped modules are suggested.

Integrated circuits (ICs) are everywhere around us. Watches we wear, television we watch, appliances we use to cook and clean, cars we drive, and computers we compute with, all have ICs in them. IC layout design topographies are a form of intellectual property since they are creations of the human intellect and they require great investments to build. Hence, there is a need for them to be protected like a property that one owns. The IC layout designs are valuable since newer developed layout designs pack more functionality in reduced dimensions with lower materials, power, and space requirements. Masks of layers of an IC capture the design layout and are used to manufacture that IC. Masks can be stolen and used to prepare photomasks for manufacturing similar ICs by those that have no right to that intellectual property. In her column “Pushing Frontiers with the First Lady of Emerging Technologies,” Dr. Satwant Kaur shows us how mask works, which are a particular type of Intellectual Property defined by the Semiconductor Chip Protection Act (SCPA), can be protected as per the US Copyright Office circulars that apply to WTO, European Community, and other countries.

On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection.