Method for Mitigating Single Event Transients in Bandgap Reference Based on Dual Modular Redundancy

Ultra-low-power (ULP) sensor technologies for the future internet of things have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various internal supply voltages, the bandgap voltage-reference (BGVR) scheme has been widely used since it provides a well-defined value with strong immunity to process/voltage/temperature variations. Nanowatt-consuming BGVR circuits have been recently proposed using a capacitor network [4] and a leakage-based proportional-to-absolute-temperature (PTAT) circuit [5]. On the other hand, the current reference circuit that is required to set internal bias current still presents difficulties in achieving both stable performance and ULP consumption. The general approach to building a current reference is to use a BGVR with additional resistors for V-to-I conversion. Though it can provide a well-defined stable current reference, it also requires excessively large resistance for ULP consumption. Another approach is a CMOS-based current reference circuit that tries to make the exponential term in the subthreshold current equation constant or temperature-independent, hence reducing process and temperature dependencies. While CMOS reference circuits have achieved ULP implementations, the current is still determined by a number of process and design parameters, resulting in large sensitivity to process variations. This paper presents a sub-10nW bandgap-reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit is implemented with a 0.18µm CMOS process and generates voltage and a current references of 1.238V and 6.64nA while consuming 9.3nW. The voltage and current references show standard deviations of 0.43% and 1.19% with temperature coefficients of 26ppm/°C and 283ppm/°C, respectively.

In this paper we describe the fault injection models for the systems tolerant to the single event upsets (SEU) and single event transients (SET). The presented fault modelling approach is based on the random generated SEU faults in sequential logic and SET faults in combinational logic. The fault injection models for triple modular redundant (TMR) and dual modular redundant (DMR) circuits are developed in order to simulate the fault-tolerant systems. The analytical models for calculation of the probability of failure-free TMR and DMR circuits are defined too. To justify the reduced redundancy concept, the simulated and calculated probabilities of failure-free TMR and DMR circuits are presented and discussed. The obtained results show a better trade-off between hardware overhead and circuit failure-free probability of the DMR concept.

In this paper, a high-precision temperature sensor designed by a standard 0.18μm CMOS process with 3.3-V power supply is presented. The CMOS temperature sensor mainly consists of a bandgap reference (BGR) circuit and a SAR ADC circuit. In the BGR circuit, not only the traditional first-order compensation technique is adopted, but also a high-order curvature correction technique is used to obtain two accurate reference voltages, which are adopted as reference voltages for the SAR ADC, and a twice emitter-base voltage of BJT is used as a temperature sensing voltage for the SAR ADC. Simulation results show that temperature coefficients of two reference voltages are as low as 1.16 ppm/°C and 3.66 ppm/°C over a temperature range of 165°C (-40°C to 125°C), PSRRs are up to −100 dB at low frequency. The CMOS temperature sensor achieves 0.1°C temperature resolution, and ±0.35°C absolute accuracy.

A high-precision current-mode bandgap reference (BGR) circuit with a high-order temperature compensation is presented in this paper. In order to achieve a high-precision BGR circuit, the equation of the nonlinear current has been modified and the high-order term of the current flowing into the nonlinear compensation bipolar junction transistor (NLCBJT) is compensated further. According to the modified equation, two solutions are designed to improve the output accuracy of BGR circuits. The first solution is to divide the NLCBJT branch into two branches to reduce the coefficient of the nonlinear temperature compensation current. The second solution is to inject the nonlinear current into the two branches based on the first one to further eliminate the temperature coefficient (TC) of the current flowing into the NLCBJT. The proposed BGR circuit has been designed using the Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The simulation results show that the variations in currents flowing into NLCBJTs improved from 148.41 nA to 69.35 nA and 7.4 nA, respectively, the TC of the output reference current of the proposed circuit is approximately 3.78 ppm/°C at a temperature range of -50 °C to 120 °C with a supply voltage of 3.3 V, the quiescent current consumption of the entire BGR circuit is 42.13 μA, and the size of the BGR layout is 0.044 mm2, leading to the development of a high-precision BGR circuit.

This paper proposes a novel curvature‐correction technique insensitive to process variations, which can be used in not only the bandgap reference (BGR) circuit but also the Zener reference circuit. By using two BJT transistors to form a differential pair structure, the current difference between the differential pair generates a compensation current, which compensates for the non‐linearity in the reference voltage. Unlike the classic curvature‐correction technique which can only be used in the BGR circuit, this novel technique can be used in the Zener reference circuit as well. What is more, the proposed curvature‐correction technique is insensitive to process variations, which greatly increases the reliability of commercial products. Finally, simulation results verify the validity of the proposed technique.

The reference voltage is a core part of RFID tags, its performance directly determines the whole chip's life and performance. The temperature coefficient is one of the important performances of the reference voltage source and the high-order temperature compensation is an effective method to reduce the temperature coefficient of the reference source. A low temperature coefficient bandgap reference is designed based on the standard 65nm CMOS process, and the low-supply voltage operation with bandgap reference circuit with current mode structure. The designed CMOS bandgap voltage reference is in the range of -20°C to 100°C with temperature coefficient of 9.6 ppm/°C and provides a good Power Supply Rejection Ratio(PSRR) of 79dB in the low frequency. The results of simulation show that the design improve the performance of the bandgap reference voltage source effectively.

The accelerated aging stress test is essential for assessing the reliability and quality of band gap reference (BGR) circuits, which are crucial for maintaining consistent voltage references in ICs. In this study, we present accelerated aging analysis of a classic BGR design as an case study. A BGR circuit, validated on a Quality and Reliability On-Chip (QROC) platform, demonstrated temperature coefficient of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.12 \text{ mV} /{}^{\circ} \mathrm{C}$</tex> across 25° C to 100° C, ensuring minimal drift with temperature fluctuations. The output reference voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{{ref}}) 646$</tex> mV was measured over a supply voltage range of 0.8V to 1.4V, with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 7.5 \text{ppm} / \mathrm{V}$</tex>. The circuit's robustness was further confirmed by observing only a 1% change in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{{ref}}$</tex> after a million-second stress test at varying temperatures and a stress voltage 1.4V. This result, showing less than 6.5% deviation from post-layout simulations, underscores the BGR's resilience and precision, highlighting the importance of such stress testing in predicting IC performance and longevity.

A novel band-gap reference circuit is presented in order to reduce the offset voltage and power consumption. By using the op-amp input voltage as part of the reference voltage source, the gain and power supply rejection ratio of the op-amp is increased. The working principle of the Band-gap reference circuit is analyzed, and it is pointed out that the temperature coefficient becomes smaller through using the temperature compensation. The simulation results based on xiyue 0.3um bipolar process show that the circuit has low power dissipation and good temperature characteristic, the power supply rejection ratio is up to 92dB. The correctness of the theoretical analysis is verified by simulation results.

A BiCMOS current source reference network which eliminates the impact of DC power supply voltage drops on the operation of ECL (emitter coupled logic) circuits is described. This is essential for implementing ECL design techniques in ULSI BiCMOS circuits. Using the current source network, reference voltages are generated locally, so that the ECL voltage references are correctly referenced to the local power supply potentials. A power-supply-insensitive bandgap reference generator is used to generate precision on-chip voltage references and current sources. The bandgap reference circuit uses both MOS and bipolar transistors and is much simpler than a similar design using bipolar-only circuitry. The micrograph of the test chip containing the bandgap circuit nd BiCMOS op amp analog drivers is shown. The drivers are designed for multiple-reference-level regeneration. The test chip has been fabricated using a 0.8- mu m BiCMOS process. The typical characteristics of the bandgap circuit and the analog driver are shown. >

This article presents a low-power bandgap reference (BGR) featuring high power supply rejection ratio (PSRR) and fast start-up capability, operating across a wide supply voltage range of 1.3–5 V. A novel prebiased pulse current injection technique is proposed in the start-up circuit, achieving a 1% settling time of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu $</tex-math> </inline-formula>s and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25\times $</tex-math> </inline-formula> speed gain during start-up. To enhance supply noise immunity, the proposed BGR employs a preregulated (PR)-based amplifier that effectively decouples the reference voltage from supply voltage fluctuations. Fabricated in a 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD process, the proposed reference occupies an active area of 0.0394 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Under a 5 V supply, the circuit generates a 1.2 V reference voltage while consuming only 48 nA quiescent current. Operating down to a minimum supply voltage of 1.3 V, it maintains a low power consumption of 57.2 nW at room temperature. The reference exhibits an average temperature coefficient (TC) of 5.95 ppm/°C across a wide temperature range (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40~^{\circ }$</tex-math> </inline-formula>C to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }$</tex-math> </inline-formula>C) and achieves an outstanding line sensitivity (LS) of 0.00308%/V over the 1.3–5 V supply range. Furthermore, the measured PSRR reaches −85 dB at 100 Hz.

A high precision band-gap reference (BGR) with piecewise-linear compensation is designed in this paper. A low voltage Brokaw BGR architecture is employed to provide low output voltage. A high gain, low power supply rejection ratio (PSRR) operational amplifier is designed to improve the PSRR of the band-gap reference. In order to achieve temperature stability significantly lower than the traditional band-gap reference, a circuit which produces a current with positive temperature coefficient (TC) at high temperatures and 0 current at lower temperatures is designed. The whole BGR circuits are simulated by Spectre based on chartered 0.18μm 1P5M 1.8V CMOS technology. It's clear from simulation result that the TC of the output reference voltage approaches 2.61ppm/K over the military temperature range, the PSRR reaches 107.2dB at low frequency (f=0.1HZ), the whole BGR dissipates 0.4mW. In addition, the output reference voltage changes only 8.6μV when the power supply changes from 1.5V to 2.1V, that is to say, the power regulation ratio is 0.014mV/V.

Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by V EB +V DS [1]. V EB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while V DS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dV GS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage V GS of subthreshold MOSFETs. Although the V GS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.

Due to the offset voltage which introduced by the mismatch and the channel-length modulation, the bandgap reference circuit in CMOS technologies is usually nonlinearly, and the design of bandgap references with high precise is a challenging circuit design problem. In this paper, we propose a method of optimizing the parameters of the components to compensate the non-linearity offset voltage using the backpropagation based neural networks. The method for training the network is investigated based on the coefficients of the input and output voltage of the circuit which make the training computationally efficient. The experimental results show that with the network structure approximation, the non-linearity of offset voltage can be reduced markedly, and the accuracy of bandgap reference is improved 10 times.

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

This paper presents a curvature-compensated bandgap reference (BGR) circuit implemented in 0.35 /spl mu/m CMOS technology. The circuit delivers an output voltage of 1.09 V and achieves a temperature coefficient of 3.1 ppm//spl deg/C over [-20/spl deg/C, 100/spl deg/C] after trimming, a power supply rejection ratio of -80 dB at 1 KHz and an output noise level of 1.43 /spl mu/V/sqrt(Hz) at 1 KHz. The BGR circuit consumes a current of 37 /spl mu/A and the power supply ranges from 1.5 V to 3.3 V.