METHODOLOGY AND BACKEND FLOW OPTIMIZATION FOR 3D

In modern IC design, circuit designers often need to manually operate and move data among different EDA (Electronic Design Automation) tools. If these tools were installed in separate computers, due to the license and system requirements, the design flow will be frequently interrupted, to handle the dreary data movement work, and the design efficiency will thus be reduced. To alleviate the above problem, a seamless and efficient design flow would be a must. The aim of this paper is to propose a service-oriented integrated EDA environment that can improve the smoothness of the design flow and consequently increase the overall design productivity. In our approach, a multi-agent framework based on JADE platform is used to manage distributed EDA tools, which are encapsulated as agent services. Mobile agents are allowed to autonomously and concurrently migrate among computers to access services for IC designers. To facilitate that, a scripting language is designed for mobile agents to allocate tasks, cooperate with each other, and select appropriate services. To demonstrate the feasibility of our method, an Integrated Circuit Design Cycle Assistant System (ICDCAS) for simplifying the manual operations in IC design cycles is developed by combining two EDA tools: ModelSim and Xilinx ISE. The implemented system proves to have the features of time saving and being free of mistakes incurred by manually operating and configuring the sophisticated EDA tools.

Over the course of 60 years, since the invention of the integrated circuit (IC), exponential improvements in cost, performance and power consumption were observed. Such advances have been strongly linked with the continuous reduction of the dimensions in manufactured ICs, but this trend has shown decreasing benefits as fundamental limits are reached. Notice that such tiny devices have increased variability, which generates unpredictable variations in the behavior of the manufactured devices. These uncertainties are typically addressed by defining margins on the clock period, estimated during the design phase. However, the overly conservative margins produce significant degradations in performance. Additionally, the evolution that enabled circuits with increasingly higher density of components, also resulted in an extremely complex IC design. At every step, electronic design automation (EDA) tools are challenged to handle this increasing complexity, requiring more powerful techniques to comply with the specification constraints within an affordable runtime. This thesis investigates alternatives in order to improve power, performance, area, and cost, using established IC manufacturing technologies. Advances in EDA are proposed in three distinct topics: area minimization using Boolean methods, area and delay reduction for designs based on fieldprogrammable gate array (FPGA), and an alternative clocking scheme to reduce timing margins. The first contribution consists of a technology-independent method for area minimization of combinational logic. Local optimization is applied on and-inverter graphs (AIGs), performing multi-output Boolean decomposition using two-literal divisors, targeting node count reduction. The second contribution regards two methods targeting technology mapping of FPGAs. On one hand, a functional decomposition approach, which uses the support size as cost function, exploring the inherent characteristics of FPGAs. On the other hand, an approach for recursive remapping, which reduces the structural bias of the subject graph, uses the mapping results as cost function, and obtains significant reductions in area and delay. The third contribution evaluates the dynamic variability mitigation and simplification of power delivery networks (PDNs) using an adaptive clocking scheme based on ring oscillator clocks (ROCs). The impact of the PDN parameters and ROC location is investigated, showing potential improvements in performance, leakage power and cost. A lo largo de los 60 años desde la invención del circuito integrado (CI), se han producido mejoras exponenciales en su coste, rendimiento y consumo de energía. Ese progreso esta fuertemente vinculado a la reducción continua de las dimensiones de fabricación de los circuitos integrados, pero esta tendencia ha ido mostrando menos beneficios a medida que se alcanzan límites fundamentales. Estos dispositivos minúsculos tienen una mayor variabilidad, lo que genera variaciones impredecibles en el comportamiento de los dispositivos fabricados. Estas incertidumbres generalmente se abordan mediante la definición de márgenes en el período de reloj, estimado durante la fase de diseño. Sin embargo, márgenes excesivamente conservadores producen degradaciones significativas en el rendimiento. Además, la evolución que permitió crear circuitos con una densidad de componentes cada vez mayor, también incrementado la complejidad de los CI. En cada paso del proceso de diseño, las herramientas de automatización de diseño electrónico (EDA) se enfrentan al desafío de manejar esta complejidad creciente, lo que requiere técnicas más potentes para cumplir con las restricciones impuestas por las especificaciónes dentro de un tiempo de ejecución asequible. Esta tesis investiga alternativas para mejorar el consumo de energía, el rendimiento, el área y el coste, utilizando las tecnologías de fabricación de CI ya establecidas. Los avances en EDA se proponen en tres temas distintos: minimización de área usando métodos booleanos, reducción de retardo y área para diseños basados en matrices de puertas programables (FPGA), y un esquema de reloj alternativo para reducir los márgenes de tiempo excesivamente conservadores. La primera contribución consiste en un método independiente de tecnología para minimizar el área de la lógica combinacional. Se aplica optimización local en grafos de AND-inversor, utilizando una descomposición Booleana de múltiples salidas con divisores de dos literales, con el objetivo de reducir la cantidad de nodos. La segunda contribución propone dos métodos para el mapeo tecnológico de los FPGA. Por un lado, un método de descomposición funcional, que utiliza el tamaño del soporte como función de coste, explorando las características inherentes de los FPGA. Por otro lado, un método de mapeo recursivo, que reduce la distorsión estructural del grafo sujeto, utiliza los resultados del mapeo como función de coste y obtiene reducciones significativas en área y retardo. La tercera contribución evalúa la mitigación de la variabilidad dinámica y la simplificación de la red de suministro de energía (PDN) utilizando un esquema de reloj adaptativo basado en un oscilador en anillo (ROC). Se investiga el impacto de los parámetros de la PDN y la ubicación del ROC, mostrando mejoras potenciales en el rendimiento, consumo estático y coste.

Provision of free, downloadable industry-standard reconfigurable hardware EDA tools is a growing and welcome trend. Low cost, ever-more-complex FPGA-based embedded system development platforms with host interface control are becoming more readily available. This paper describes a series of structured VHDL workshop modules which use the Xilinx ISE Webpack/ModelsimXE electronic design automation (EDA) tools and Digilent Spartan-3 hardware development system. The described course implements an extendable embedded system, which performs a selection of image and audio processing applications, controlled by a host graphical user interface (GUI). A formal structured design, documentation and test methodology is incorporated throughout the course. Enhancements to EDA tool VHDL and diagram creation wizard support are proposed to aid VHDL capture automation and design visualisation. Improved student understanding and achievement level in VHDL programming, digital embedded system design techniques and FPGA implementation has resulted

Due to the trend of globalized semiconductor supply chain, integrated circuits (IC) and hardware intellectual property (IP) are prone to serious security threats such as reverse engineering and IP piracy. In addition to the post-fabrication authentication techniques (e.g., IP metering), various hardware hardening approaches have emerged to resist reverse engineering and IP piracy. This chapter reviews three representable security hardening approaches—camouflaging, logic encryption/locking, and design obfuscation—that are applied to ICs at layout, gate, and register transfer levels. Particularly, this chapter presents a dynamic state-deflection-based obfuscation method, which deflects the state transition from the original transition path to a black hole cluster if an invalid key is applied to the hardware IP. This obfuscation method can successfully thwart the reverse engineering attack that exploits the code analysis support from electronic design automation (EDA) tools. Furthermore, this chapter extends the idea of design obfuscation for two-dimensional IC to emerging three-dimensional (3D) IC design technology. The proposed method is based on the insertion of a Network-on-Chip (NoC)-based shielding plane between two commercial dies to build the secure 3D ICs without involvement of trustworthy foundries.

Layout generation is the task of the analog integrated circuit (IC) design flow that both lays the devices (i.e., placement), whose dimensions were previously determined for the selected topology, out in the chip and connects them (i.e., routing), creating the masks for future manufacturing. In this chapter, exploratory research using artificial neural networks (ANNs) is conducted to automate the placement task of analog IC layout design. The proposed methodology abstracts the need to explicitly deal with topological constraints by learning reusable design patterns from validated legacy layout designs. The ANNs are trained on a dataset of an analog amplifier containing thousands of placement solutions for 12 different and conflicting layout styles/guidelines and used to output different placement alternatives, for sizing solutions outside the training set, at push-button speed. Ultimately, the methodology can offer the opportunity to reuse all the existent legacy layout information, either generated by layout designers or electronic design automation (EDA) tools. In the first section of this chapter, the novel ideas proposed by this methodology are outlined. Additional detail on the circuit used to demonstrate the methodology, how the dataset is structured, the general architecture of the proposed ANN, and metrics used to evaluate the models is provided in Sect. 5.2. Afterward, in Sect. 5.3, the tests conducted to assess the viability of using an ANN to automatically generate analog IC layout placements are fully detailed. In Sect. 5.4, the conclusions taken from the developments described in this chapter and future research directions are outlined.

Recent developments in EDA tools for power electronics modules have led to simultaneous analysis and optimization of package features with regard to electro-thermal and thermo-mechanical aspects. In this work, two of these EDA tools, PowerSynth and ParaPower, are linked together with a software application programming interface (API) to rapidly explore a combined electro-thermo-mechanical design space and present the user with co-optimized solutions and tradeoffs in a fraction of the time consumed using traditional analysis methods. An overview of this co-design process and its advantages over that of the traditional, iterative approach is presented along with an explanation of the methods used by the respective tools for analysis. Finally, additional considerations and constraints are introduced that ensure manufacturing feasibility and reliable operation at high voltages. A case study in co-design using these tools has been proposed for the final paper.

Advanced electronic design automation (EDA) tools, with their simulation, modeling, design rule checking, and optical proximity correction capabilities, have facilitated the improvement of first pass wafer yields. While the data produced by these tools may have been processed for optimal wafer manufacturing, it is possible for the same data to be far from ideal for photomask manufacturing, particularly at lithography and inspection stages, resulting in production delays and increased costs. The same EDA tools used to produce the data can be used to detect potential problems for photomask manufacturing in the data. A production implementation of automated photomask manufacturing rule checking (MRC) is presented and discussed for various photomask lithography and inspection lines. This paper will focus on identifying data which may cause production delays at the mask inspection stage. It will be shown how photomask MRC can be used to discover data related problems prior to inspection, separating jobs which are likely to have problems at inspection from those which are not. Photomask MRC can also be used to identify geometries requiring adjustment of inspection parameters for optimal inspection, and to assist with any special handling or change of routing requirements. With this foreknowledge, steps can be taken to avoid production delays that increase manufacturing costs. Finally, the data flow implemented for MRC can be used as a platform for other photomask data preparation tasks.

With the increased level of complexity and market pressures to deliver better results faster and cheaper, Integrated Circuit (IC) companies are looking to innovate and introduce efficiencies into their development process. To improve IC design productivity and time-to-market, this paper introduces an innovative Electronic Design Automation (EDA) tool in order to replicate an existing layout in different technology nodes by automatically porting analog and mixed-signal circuits. Furthermore, the paper presents a case study of the application of the Methodology Assessment Framework (MAF) as an evaluation tool to choose the best suited Software Development Methodology (SDM) for the EDA tool development project.

Digital Electronic Design Automation (EDA) tools have seen a remarkable improvement over the last decade. In addition to providing good documentation, their ability to simulate a design provides immense convenience in optimizing a design and in examining what-if scenarios which would otherwise be very time-consuming, expensive, and even impossible using hardware. This paper begins with an overview of EDA tools and related issues. Next, it discusses the implementation of an EDA laboratory established with funding from the National Science Foundation. Details of four experiments and an evaluation of the EDA tools used in the undergraduate curriculum have been presented.

The incorporation of electronic design automation (EDA) tools in engineering curricula will better prepare graduates to enter the modern engineering marketplace. The engineering courses appropriate for EDA introduction are discussed, as are the tools themselves and their sources. Issues of computing platform, operating system, and tool suites are presented. Internet accessible public domain documents are provided to aid engineering schools in setting up a comprehensive EDA curriculum.

This work addresses the use of Electronic Design Automation (EDA) tools for topology selection and optimal sizing of Voltage Controlled Oscillator (VCO) Integrated Circuits (ICs). Instead of relying on empirical data and closed form equations to select device sizes, a simulation-based approach is adopted for better accuracy. By using an optimization method based on Evolutionary Algorithms (EAs) in combination with a tool for parametrized schematic simulations, we are able to asses the attainable performance trade-offs for different topologies and oscillation frequencies. We use Cadence Spectre for simulations and demonstrate our approach on two cross-coupled LC-VCO topologies by providing with Pareto optimal Fronts.

As the semiconductor industry moves into the next generation sub-nanometer design the quality of the electronic design automation (EDA) tools becomes more critical. With shrinking market windows and increasing time to market constraints the designers need reliable and robust EDA software tools to ensure that the design is manufacturable with an acceptable yield. This paper develops a balanced scorecard for implementing systemic quality in an EDA organization.

This paper presents a project‐based learning approach to improve students' ability to apply systematic design methodologies during their transition from general Electrical Engineering (EE) courses to Integrated Circuit (IC) design programs. With the advent of Electronic Design Automation (EDA) tools and Artificial Intelligence (AI) techniques, there is a growing need for students to develop a more systematic understanding of circuit design. A structured training program is designed to enhance the ability of mixed IC design of fourth‐year students, who are expected to use open source tools to design key circuit components which are aligned with MATLAB. With these components, the mixed signal system can be built and optimized top‐down, allowing significantly accelerated development and deeper knowledge learning. A team of students is required to design MATLAB‐aligned circuit components and a benchmark testing framework is developed to ensure the alignment of functionality between the proposed work and MATLAB Simulink. The results indicate that the proposed project‐based learning approach effectively supports fourth‐year students in transitioning to IC design, with strong recommendations for its continued implementation in future academic years. The project establishes a comprehensive and free EDA framework for teaching mixed signal IC design, offering significant advantages over traditional commercial tools. Moreover, the use of hardware‐defined code provides greater flexibility in the design environment, allowing students to utilize the EDA framework across multiple platforms without the need for expensive commercial licenses.

The microcontroller unit (MCU) are mainly used in low power devices, which use limited energy sources such as batteries, energy harvesting, and wireless communications. Therefore, reducing the operating power of the MCU is important to improve energy efficiency by extending battery life or minimizing energy consumption. The MCU is one of the chip designs composed of digital integrated circuits. The clock signal is important element to the MCU. The clock tree, which consists of the clock signal, is directly related to MCU low power operation and performance improvement. Also, chip verification process is important role to improve performance of overall system and reliability to the MCU. However, as the degree of integation of chips, the chip verification process increases complexity and time-comsumption to process many data. Currently, many users dependent on licensed electronic design automation (EDA) tools to ensure high accuracy, minimizing errors in circuit design and improving reliability. The use of licensed EDA tool puts a burden on users including high costs, limited license, difficulty in customization, slow speed, etc. An effective approach to avoid problems by using licensed EDA tools proceeds verification that is unrestricted license and customization for possible using only a register transfer level (RTL) source. In this paper, we propose to predict roughly pre-estimated CTS results using an RTL source in which temporary logic using random buffer insertion is placed before the route process. This paper contributes to reducing MCU operating power and hardware area by performing optimized CTS and minimizing resources according to the RTL structure to be designed.

As semiconductor technology continues to advance at an unprecedented pace, the integration of smaller and more densely packed transistors on silicon wafers has ushered in an era of unrivaled power and energy efficiency. However, this rapid advancement also introduces a significant and growing challenge: the increasing problem of process variation. Variations in manufacturing processes, device characteristics, and environmental conditions can result in large changes to performance and reliability for integrated circuits (IC). These variations introduce substantial hurdles to achieving predictable timing performance in modern electronic systems. This work delves into the multifaceted issue of process variation and presents a novel, variation-aware clock tree synthesis methodology (Var-CTS) to address that variation. Var-CTS is used during the initial synthesis stage of physical design to improve the statistical worst case timing. Using a timing library characterized for variation, the methodology uses variation-aware merging regions for skew that improve timing and resilience against variation. Building up to the variation-aware clock tree synthesis, two studies for clock slew and wiring type are performed and one methodology considering bounded clock tree synthesis is presented. The first study explores the effects of slew on clock power and timing. The study shows that slew constraint manipulation can improve power consumption while maintaining high-performance operation. A study of a uniquely fundamental wiring type is performed that can improve routing density, an important aspect for reducing wire variations during manufacturing. The implemented wiring type is determined to have positive effects on both the timing of the implemented clock trees with the added consideration of routing density. A bounded skew and slew merging region methodology for clock tree synthesis is presented to improve performance of the implemented clock tree. The methodology shows improvement over previous research due to multi-constraint merging regions during the clock tree synthesis merging process. Finally, the variation-aware clock tree synthesis methodology is presented. Results from Monte Carlo-based simulations show how including statistical timing information in the clock tree synthesis methodology improves the final statistical worst-case skew variation of a high-performance clock tree.